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1. 发明授权

US06895458B2 Opcode to turn around a bi-directional bus 有权
标题翻译：操作代码转向双向总线
公开(公告)号：US06895458B2
公开(公告)日：2005-05-17
申请号：US10090491
申请日：2002-03-04
申请人： Ewa M. Kubalska , Lisa Grenier , Yan Yan Tang , Elena M. Ing
发明人： Ewa M. Kubalska , Lisa Grenier , Yan Yan Tang , Elena M. Ing
IPC分类号： G06F13/36 , G06T15/00 , G09G5/36 , G06F13/00
CPC分类号： G09G5/363 , G06F13/36 , G06T15/005
摘要： A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data bus. If the master is in a bus driving state (with respect to the data bus) and receives a read request, the master relinquishes bus control and sends a read request through the request opcode bus. The slave unit assumes bus control and sends the requested data through the data bus. If the master is in a bus sensing state and receives a write request, the master sends a last read opcode to the slave via the request opcode bus, and waits for the slave to return a special token through the reply opcode bus. Upon receiving the special token the master unit assumes bus control and performs the write transaction.
摘要翻译：一种用于管理主单元和从单元之间的双向数据总线的控制的系统。主机通过请求操作码总线，应答操作码总线和数据总线耦合到从机。如果主机处于总线驱动状态（相对于数据总线）并接收到读取请求，则主机放弃总线控制并通过请求操作码总线发送读取请求。从单元假设总线控制，并通过数据总线发送所请求的数据。如果主机处于总线感测状态并接收写请求，则主机通过请求操作码总线向从机发送最后一个读操作码，并等待从机通过应答操作码总线返回特殊令牌。在接收到特殊令牌时，主单元承担总线控制并执行写入事务。

2. 发明授权

US06661423B2 Splitting grouped writes to different memory blocks 有权
标题翻译：将分组写入分成不同的内存块
公开(公告)号：US06661423B2
公开(公告)日：2003-12-09
申请号：US09861184
申请日：2001-05-18
申请人： Michael G. Lavelle , Ewa M. Kubalska , Elena M. Ing
发明人： Michael G. Lavelle , Ewa M. Kubalska , Elena M. Ing
IPC分类号： G06F1206
CPC分类号： G06T1/60
摘要： A memory array management unit suitable for use in a computer graphics system is described. The unit is especially designed to facilitate the storage of tiles of graphics data. Alignment detection between the tiles and memory block boundaries is provided for, with misalignments resulting in the automatic decimation to produce sub-tiles and generation of multiple memory write sequences.
摘要翻译：描述适用于计算机图形系统的存储器阵列管理单元。该单元特别设计用于方便存储图形数据的瓦片。提供了瓦片和存储器块边界之间的对准检测，其中未对准导致自动抽取以产生子图块并生成多个存储器写入序列。

3. 发明授权

US08134570B1 System and method for graphics attribute packing for pixel shader usage 有权
标题翻译：用于像素着色器使用的图形属性打包的系统和方法
公开(公告)号：US08134570B1
公开(公告)日：2012-03-13
申请号：US11532779
申请日：2006-09-18
申请人： Jerome F. Duluk, Jr. , Andrew J. Tao , Roger L. Allen , Svetoslav D. Tzvetkov , Yan Yan Tang , Elena M. Ing
发明人： Jerome F. Duluk, Jr. , Andrew J. Tao , Roger L. Allen , Svetoslav D. Tzvetkov , Yan Yan Tang , Elena M. Ing
IPC分类号： G09G5/00
CPC分类号： G06T15/005
摘要： A system, method and computer program product are provided for packing graphics attributes. In use, a plurality of graphics attributes is identified. Such graphics attributes are packed, such that the packed graphics attributes are capable of being processed utilizing a pixel shader.
摘要翻译：提供了用于打包图形属性的系统，方法和计算机程序产品。在使用中，识别出多个图形属性。打包这样的图形属性，使得打包的图形属性能够利用像素着色器进行处理。

4. 发明授权

US06819320B2 Reading or writing a non-super sampled image into a super sampled buffer 有权
标题翻译：将非超级采样图像读入或写入超采样缓冲器
公开(公告)号：US06819320B2
公开(公告)日：2004-11-16
申请号：US10090479
申请日：2002-03-04
申请人： Michael G. Lavelle , Elena M. Ing
发明人： Michael G. Lavelle , Elena M. Ing
IPC分类号： G06F1500
CPC分类号： G06T5/002 , G06T5/20 , G06T2200/12 , G06T2207/10016
摘要： A graphics system and method for storing pixel values into or reading pixel values from a sample buffer, wherein the sample buffer is configured to store a plurality of samples for each of a plurality of pixels. The graphics system comprises a sample buffer, a programmable register, and a graphics processor. The programmable register stores a value indicating a method for pixel to sample conversion, and is preferably software programmable (e.g., user programmable). The graphics processor accesses the memory to determine a method for pixel to sample conversion and stores the pixel values in the sample buffer according to the determined method. A first method for pixel to sample conversion may specify a pixel write to all of the pixel's supporting samples. A second method for pixel to sample conversion may specify a pixel write to a selected one of the pixel's supporting samples.
摘要翻译：一种用于将像素值存储到样本缓冲器中或从其中读取像素值的图形系统和方法，其中所述采样缓冲器被配置为存储多个像素中的每一个的多个采样。图形系统包括采样缓冲器，可编程寄存器和图形处理器。可编程寄存器存储指示用于像素到样本转换的方法的值，并且优选地是软件可编程的（例如，用户可编程的）。图形处理器访问存储器以确定用于像素进行采样转换的方法，并根据确定的方法将像素值存储在采样缓冲器中。用于像素进行采样转换的第一种方法可以指定对所有像素的支持样本的像素写入。用于像素到采样转换的第二种方法可以指定对所选像素的支持样本中的所选择的像素的像素写入。

5. 发明授权

US06864900B2 Panning while displaying a portion of the frame buffer image 有权
标题翻译：在显示帧缓冲图像的一部分的同时平移
公开(公告)号：US06864900B2
公开(公告)日：2005-03-08
申请号：US09861467
申请日：2001-05-18
申请人： Michael A. Wasserman , Michael G. Lavelle , Elena M. Ing
发明人： Michael A. Wasserman , Michael G. Lavelle , Elena M. Ing
IPC分类号： G06F3/14 , G09G5/34 , G09G5/36 , G09G5/00
CPC分类号： G09G5/363 , G06F3/1431 , G09G5/346
摘要： A graphics system and method for panning from one portion of a stored image to another portion of the image includes a frame buffer, one or more display devices, one or more raster parameter registers, and one or more raster parameter updaters. The image is stored in the frame buffer and each display device is configured to display less than the entire image. A panning operation is initiated by requesting an update of one or more of the raster parameter registers during a next blanking period.
摘要翻译：用于从存储的图像的一部分平移到图像的另一部分的图形系统和方法包括帧缓冲器，一个或多个显示设备，一个或多个光栅参数寄存器以及一个或多个光栅参数更新器。图像被存储在帧缓冲器中，并且每个显示设备被配置为显示小于整个图像。通过在下一个消隐期间请求更新一个或多个光栅参数寄存器来启动平移操作。

6. 发明授权

US06940514B1 Parallel initialization path for rasterization engine 有权
标题翻译：光栅化引擎的并行初始化路径
公开(公告)号：US06940514B1
公开(公告)日：2005-09-06
申请号：US10831972
申请日：2004-04-26
申请人： Michael A. Wasserman , Elena M. Ing , Vannessa M. Nhan , Nandini Ramani , Charles P. Chang
发明人： Michael A. Wasserman , Elena M. Ing , Vannessa M. Nhan , Nandini Ramani , Charles P. Chang
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A system and method are disclosed for a rasterization pipeline with a parallel initialization path that may provide an increased rate of triangle processing. The edge walker, span walker, and sample generator modules of a rasterization pipeline may be modified to enable the next primitive in the sequence of primitives to be initialized, while the current primitive is processed. Consequently, these two processes that were done in series may now be done in parallel. Data transmitted between modules may be separated into initialization data (data the module needs to define a primitive) and primitive data (the processed output of each module). The second path is for additional initialization data, which allows each of these modules to receive the initialization data for the next primitive, while processing the primitive data for the current primitive.
摘要翻译：公开了一种具有可提供增加的三角形处理速率的并行初始化路径的光栅化流水线的系统和方法。光栅化流水线的边缘步行者，跨越步行者和样本发生器模块可以被修改，以使原始序列中的下一个原语被初始化，同时处理当前的基元。因此，串联完成的这两个过程现在可以并行进行。在模块之间传输的数据可以分为初始化数据（模块需要定义原语的数据）和原始数据（每个模块的处理输出）。第二条路径是用于额外的初始化数据，它允许这些模块中的每一个接收下一个原语的初始化数据，同时处理当前图元的原始数据。

7. 发明授权

US06836272B2 Frame buffer addressing scheme 有权
标题翻译：帧缓冲器寻址方案
公开(公告)号：US06836272B2
公开(公告)日：2004-12-28
申请号：US10096066
申请日：2002-03-12
申请人： Philip C. Leung , Michael G. Lavelle , Elena M. Ing
发明人： Philip C. Leung , Michael G. Lavelle , Elena M. Ing
IPC分类号： G09G5399
CPC分类号： G09G5/39 , G09G5/14 , G09G2360/121 , G09G2360/126
摘要： A graphics system includes a frame buffer that includes one or more memory devices and a frame buffer interface coupled to the frame buffer. Each memory device in the frame buffer includes N banks. Each of the N banks includes multiple pages, and each page is configured to store data corresponding to a portion of a screen region. The frame buffer interface is configured to generate address used to store data corresponding to a frame of data in the frame buffer. The frame includes multiple screen regions. The frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer. The addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions.
摘要翻译：图形系统包括帧缓冲器，其包括一个或多个存储器设备和耦合到帧缓冲器的帧缓冲器接口。帧缓冲器中的每个存储器件包括N个存储体。每个N个存储体包括多个页面，并且每个页面被配置为存储对应于屏幕区域的一部分的数据。帧缓冲器接口被配置为生成用于存储对应于帧缓冲器中的数据帧的数据的地址。该框架包括多个屏幕区域。帧缓冲器接口被配置为生成与该数据相对应的地址，并且向帧缓冲器提供地址。生成地址，使得N个存储体中的每一个存储对应于屏幕区域的水平组内的每N个屏幕区域中的一个的一部分的数据。

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