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1. 发明授权

US06803917B2 Checkerboard buffer using memory bank alternation 有权
标题翻译：使用存储库交替的棋盘缓冲区
公开(公告)号：US06803917B2
公开(公告)日：2004-10-12
申请号：US09908301
申请日：2001-07-17
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5399
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/399 , G09G2352/00 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132 , H04N21/44004
摘要： Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels for one frame is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. While data is being stored, data for pixels from another frame is retrieved from another two memory devices. The banks of devices alternate between storing and retrieving with each frame. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to at least two memory devices and retrieved in parallel from at least two memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
摘要翻译：用于并行存储数据并以不同顺序检索数据的方法和装置。在一个实现中，一帧的像素的数据根据棋盘图案交替地存储在两个存储器件之间，形成棋盘缓冲器。当存储数据时，从另外两个存储器件检索来自另一帧的像素的数据。设备库在每个帧之间交替存储和检索。在一个实现中，棋盘缓冲器包括：数据源，以第一顺序提供数据; 数据目的地，以二次接收数据; 至少四个存储器设备，每个存储器设备具有多个存储器位置，其中数据与至少两个存储器设备并行存储并且从至少两个存储器设备并行检索; 连接到数据源和每个存储器件的第一数据开关，其中第一数据开关控制将哪个数据存储到哪个存储器件; 以及连接到数据目的地和每个存储设备的第二数据交换机，其中第二数据交换机根据第二级控制向数据目的地提供数据。

2. 发明授权

US06522335B2 Supplying data to a double buffering process 有权
标题翻译：将数据提供给双缓冲过程
公开(公告)号：US06522335B2
公开(公告)日：2003-02-18
申请号：US09307736
申请日：1999-05-10
申请人： Eric Brown
发明人： Eric Brown
IPC分类号： G09G5399
CPC分类号： G06F1/3225 , G09G5/399
摘要： Data is supplied to a double buffering process. New data is supplied to a background buffer for a displayed item. A condition is identified to the effect that the item in a foreground buffer is invalid. On the previous cycle, a similar process may have been performed such that the background buffer contains invalid items. Before swapping the roles of the buffers, any invalid items in the background buffer are validated. In this way, all item transitions appear without artefacts without adding a significant overhead.
摘要翻译：数据提供给双缓冲过程。新数据将提供给显示项目的后台缓冲区。识别出前台缓冲区中的项目无效的条件。在上一个循环中，可能已经执行了类似的过程，使得后台缓冲器包含无效项。在交换缓冲区的角色之前，验证后台缓冲区中的任何无效项。这样，所有项目转换都不会出现伪像，而不会增加显着的开销。

3. 发明授权

US06831650B2 Checkerboard buffer using sequential memory locations 有权
标题翻译：棋盘缓冲区使用顺序存储位置
公开(公告)号：US06831650B2
公开(公告)日：2004-12-14
申请号：US09907852
申请日：2001-07-17
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5399
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/399 , G09G2352/00 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132 , H04N21/44004
摘要： Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices, and where data is stored according to the first order using sequential memory locations in the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
摘要翻译：用于并行存储数据并以不同顺序检索数据的方法和装置。在一个实现中，用于像素的数据根据棋盘图案交替存储在两个存储器件之间，形成棋盘缓冲器。在一个实现中，棋盘缓冲器包括：数据源，以第一顺序提供数据; 数据目的地，以二次接收数据; 至少两个存储器设备，每个存储器设备具有多个存储器位置，其中数据与存储器设备并行存储并且从存储器设备并行检索，并且其中根据第一顺序存储数据，使用顺序存储器位置存储器件; 连接到数据源和每个存储器件的第一数据开关，其中第一数据开关控制将哪个数据存储到哪个存储器件; 以及连接到数据目的地和每个存储设备的第二数据交换机，其中第二数据交换机根据第二级控制向数据目的地提供数据。

4. 发明授权

US06760034B2 Three dimensional display emulation method and system 失效
标题翻译：三维显示仿真方法及系统
公开(公告)号：US06760034B2
公开(公告)日：2004-07-06
申请号：US10017769
申请日：2001-10-30
申请人： Olivier F. Prache
发明人： Olivier F. Prache
IPC分类号： G09G5399
CPC分类号： H04N13/261 , H04N13/344
摘要： A stereoscopic display device includes a pair of OLED microdisplays in a Head Mounted Display. An emulation video signal is provided to the display device. The emulation video signal includes alternating frames of left and right video data. An enable signal is provided to the left and right displays to control when image data in the display is updated so as to update data with corresponding frame data of the emulation signal. The updating of data in the combined display is at the standard rate while the updating of data in each display is at half the standard rate.
摘要翻译：立体显示装置包括头戴式显示器中的一对OLED微型显示器。向显示装置提供仿真视频信号。仿真视频信号包括左右视频数据的交替帧。向左右显示器提供使能信号，以控制显示器中的图像数据被更新以便更新具有仿真信号的相应帧数据的数据。组合显示中的数据更新是标准速率，而每个显示器中的数据更新是标准速率的一半。

5. 发明授权

US06831651B2 Checkerboard buffer 有权
标题翻译：棋盘缓冲区
公开(公告)号：US06831651B2
公开(公告)日：2004-12-14
申请号：US09908295
申请日：2001-07-17
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5399
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/399 , G09G2352/00 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132 , H04N21/44004
摘要： Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
摘要翻译：用于并行存储数据并以不同顺序检索数据的方法和装置。在一个实现中，用于像素的数据根据棋盘图案交替地存储在两个存储器件之间，形成棋盘缓冲器。在一个实现中，棋盘缓冲器包括：数据源，以第一顺序提供数据; 数据目的地，以二次接收数据; 至少两个存储器设备，每个存储器设备具有多个存储器位置，其中数据与存储器设备并行存储并且从存储器设备并行检索; 连接到数据源和每个存储器件的第一数据开关，其中第一数据开关控制将哪个数据存储到哪个存储器件; 以及连接到数据目的地和每个存储设备的第二数据交换机，其中第二数据交换机根据第二顺序控制向数据目的地提供数据。

6. 发明授权

US06801205B2 Method for reducing transport delay in a synchronous image generator 有权
标题翻译：减少同步图像发生器传输延迟的方法
公开(公告)号：US06801205B2
公开(公告)日：2004-10-05
申请号：US09731683
申请日：2000-12-06
申请人： Harold Dee Gardiner , Steve O. Hadfield
发明人： Harold Dee Gardiner , Steve O. Hadfield
IPC分类号： G09G5399
CPC分类号： G09G5/399
摘要： A method for enabling reduced transport display in a computer image generator connected to a host simulator which receives real-time input. The first step is performing real-time matrices calculations with the real-time input. The next step is processing geometry for primitives in a scene and storing the primitives in a double-buffered geometry buffer. The geometry buffer toggles as soon as the geometry processing is done without waiting for a field sync signal which reduces the transport delay normally found in image generation systems. Another step is rendering the primitives into a pixel frame buffer as soon as the geometry buffer toggles. The final step is displaying the pixel frame buffer. The rendering hardware and geometry processing hardware can also include enough processing power to complete the geometric transformations and rendering and in less than one display frame. Allowing the geometry and rendering to complete faster allows reduces the transport delay because the geometry buffer can toggle sooner and the pixels can be displayed sooner.
摘要翻译：一种用于在连接到接收实时输入的主机模拟器的计算机图像生成器中实现减少的传输显示的方法。第一步是使用实时输入进行实时矩阵计算。下一步是处理场景中原语的几何，并将原语存储在双缓冲几何缓冲区中。一旦几何处理完成，几何缓冲区即可切换，而不必等待一个字段同步信号，减少通常在图像生成系统中发现的传输延迟。一旦几何缓冲区切换，另一步就是将图元渲染成像素帧缓冲区。最后一步是显示像素帧缓冲区。渲染硬件和几何处理硬件还可以包括足够的处理能力来完成几何变换和渲染以及在不到一个的显示框架内。允许几何和渲染完成更快可以减少传输延迟，因为几何缓冲区可以更快地切换，并可以更快地显示像素。

7. 发明授权

US06496192B1 Modular architecture for image transposition memory using synchronous DRAM 失效
标题翻译：使用同步DRAM的图像转置存储器的模块化架构
公开(公告)号：US06496192B1
公开(公告)日：2002-12-17
申请号：US09368626
申请日：1999-08-05
申请人： Vasanth Shreesha , David Nasoff
发明人： Vasanth Shreesha , David Nasoff
IPC分类号： G09G5399
CPC分类号： G06T1/60 , H04N5/2628
摘要： A memory architecture for a video transpose memory employs SDRAM memory devices which are arranged in memory rows such that elements in a single row may be accessed without memory set-up latency. The memory architecture includes at least two memory banks such that memory write operations to one bank may be interleaved with memory write operations to the other bank. Samples of the image along one direction are stored into the memory in groups such that corresponding samples in the orthogonal direction are held in the same memory row. The memory banks are interleaved on the store operation such that consecutive write operations access respective memory rows in the alternating memory banks. The number of samples in a group of samples is selected such that the total time for displaying the number of samples in the group is at least equal to the set-up latency of the memory. Accordingly, consecutive groups of samples may be stored into the alternating memory banks continuously. When image data are read from memory, the memory read operations are not interleaved. To compensate for the set-up latency in the read operations, the controller advances the first read operation for a particular image line or image column into the horizontal or vertical blanking interval by an amount of time equal to the total latency for the line or column. The system includes a first in first out (FIFO) buffer which receives the image data as it is provided from the memory in response to the memory read requests and provides the image data according to the output timing for the transpose memory.
摘要翻译：用于视频转置存储器的存储器架构使用布置在存储器行中的SDRAM存储器件，使得可以在没有存储器建立延迟的情况下访问单行中的元件。存储器架构包括至少两个存储器组，使得对一个存储体的存储器写入操作可以与对另一个存储体的存储器写入操作进行交织。沿着一个方向的图像的样本被分组地存储在存储器中，使得正交方向上的相应样本保持在相同的存储行中。存储体在存储操作中交错，使得连续的写操作访问交替存储体中的各个存储行。选择一组样本中的样本数，使得显示该组中的样本数的总时间至少等于存储器的设置等待时间。因此，连续的采样组可以连续存储在交替存储体中。当从存储器读取图像数据时，存储器读取操作不被交织。为了补偿读取操作中的设置延迟，控制器将特定图像行或图像列的第一读取操作前进到水平或垂直消隐间隔等于线或列的总延迟的时间量。该系统包括先进先出（FIFO）缓冲器，其响应于存储器读取请求从存储器接收图像数据，并根据转置存储器的输出定时提供图像数据。

8. 发明授权

US06806884B2 Technique for filling a region of memory using multiple region fill processors 失效
标题翻译：使用多个区域填充处理器填充内存区域的技术
公开(公告)号：US06806884B2
公开(公告)日：2004-10-19
申请号：US09963226
申请日：2001-09-25
申请人： Roy Troutman , Calvin Selig
发明人： Roy Troutman , Calvin Selig
IPC分类号： G09G5399
CPC分类号： G06T1/60
摘要： A technique for filling a memory area that represents a rectangle. The rectangle or a first section thereof may be divided into i+j horizontal subsections. The i horizontal subsections may be filled in a first pass using i region fill processors. And the j horizontal subsections may be filled in a second pass using j region fill processors. A second section of the rectangle may be filled by dividing the second section into n vertical subsections having equal width and filling the n vertical subsections using n region fill processors.
摘要翻译：一种用于填充表示矩形的存储区域的技术。矩形或其第一部分可以被划分为i + j个水平子部分。可以使用i区域填充处理器在第一遍中填充i个水平子部分。并且j个水平子部分可以使用j个区域填充处理器填充在第二遍中。可以通过将第二部分划分成具有相等宽度的n个垂直子部分并且使用n个区域填充处理器填充n个垂直子部分来填充该矩形的第二部分。

9. 发明授权

US06791538B2 Method and system for operating a combination unified memory and graphics controller 失效
标题翻译：操作组合统一存储器和图形控制器的方法和系统
公开(公告)号：US06791538B2
公开(公告)日：2004-09-14
申请号：US09955649
申请日：2001-09-18
申请人： Henricus Antonius Gerardus Van Vugt
发明人： Henricus Antonius Gerardus Van Vugt
IPC分类号： G09G5399
CPC分类号： G09G5/399 , G09G2320/103 , G09G2340/02 , G09G2360/125
摘要： A display-based system is disclosed with a processing unit, a memory control facility, and a graphics display controller interfacing to a display facility. Collectively these modules are interconnected by a bus facility to an external memory facility. The graphics display controller has a first mode providing a video image signal to the display facility. In particular, a detector is provided for detecting display stabilization. An output of the graphics display controller is being coupled to a frame grabber. The frame grabber is arranged to execute a writeback-to-memory storage of the video image signal into a writeback image memory during a subsequent videoframe, and subsequently signaling the graphics display controller to switch over to a second mode, in which the stored writeback video image signal is supplied to the display facility. The average data traffic on the bus facility is thus reduced.
摘要翻译：公开了一种基于显示器的系统，其具有处理单元，存储器控制设备和与显示设备接口的图形显示控制器。总的来说，这些模块通过总线设施互连到外部存储设备。图形显示控制器具有向显示设备提供视频图像信号的第一模式。特别地，提供了用于检测显示稳定性的检测器。图形显示控制器的输出被耦合到帧采集器。帧抓取器被布置为在随后的视频帧期间执行视频图像信号的写回存储器存储到写回图像存储器中，并且随后发信号通知图形显示控制器切换到第二模式，其中存储的回写视频图像信号被提供给显示设施。因此，公交车设施上的平均数据流量减少了。

10. 发明授权

US06741256B2 Predictive optimizer for DRAM memory 有权
标题翻译： DRAM内存的预测优化器
公开(公告)号：US06741256B2
公开(公告)日：2004-05-25
申请号：US09940233
申请日：2001-08-27
申请人： Brian D. Emberling
发明人： Brian D. Emberling
IPC分类号： G09G5399
CPC分类号： G06T1/60 , G09G5/026 , G09G5/363 , G09G5/39 , G09G2360/02 , G09G2360/122 , G09G2360/123
摘要： A predictive optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves.
摘要翻译：描述了一种用于交错存储器并适用于计算机图形系统的预测优化单元。该单元维护来自存储器的数据待处理请求的队列，并优先处理预先充电并激活具有未决请求的交错。处于就绪状态的交织可以独立于非就绪交错的预充电和激活来访问。

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