专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120297128A1 REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS 有权
标题翻译：在基于闪存的存储器系统中减少访问内容
公开(公告)号：US20120297128A1
公开(公告)日：2012-11-22
申请号：US13563947
申请日：2012-08-01
申请人： Evangelos S. Eleftheriou , Robert Haas , Peter Mueller , Roman A. Pletka
发明人： Evangelos S. Eleftheriou , Robert Haas , Peter Mueller , Roman A. Pletka
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.
摘要翻译：示例性实施例包括一种用于减少基于闪存的存储器系统中的访问争用的方法，该方法包括从具有多个信道的存储器件和多个存储器块中选择处于空闲状态的芯片条带，其中芯片条带包括多个页面，将所述条纹设置为写入状态，为所述多个通道中的每一个设置所述多个通道中的每一个中的写入队列头部，将所述写入队列头部设置到所述第一自由页面中的第一自由页面属于来自芯片条带的信道的芯片，根据写入分配调度器在信道之间分配写请求，产生页写入，并响应于页写，增加写队列头，并将片段条设置为on 线状态当它满了。

2. 发明申请

US20110145475A1 REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS 有权
标题翻译：在基于闪存的存储器系统中减少访问内容
公开(公告)号：US20110145475A1
公开(公告)日：2011-06-16
申请号：US12637897
申请日：2009-12-15
申请人： Evangelos S. Eleftheriou , Robert Haas , Peter Mueller , Roman A. Pletka
发明人： Evangelos S. Eleftheriou , Robert Haas , Peter Mueller , Roman A. Pletka
IPC分类号： G06F12/00 , G06F12/10 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.
摘要翻译：示例性实施例包括一种用于减少基于闪存的存储器系统中的访问争用的方法，该方法包括从具有多个信道的存储器件和多个存储器块中选择处于空闲状态的芯片条带，其中芯片条带包括多个页面，将所述条纹设置为写入状态，为所述多个通道中的每一个设置所述多个通道中的每一个中的写入队列头部，将所述写入队列头部设置到所述第一自由页面中的第一自由页面属于来自芯片条带的信道的芯片，根据写入分配调度器在信道之间分配写请求，产生页写入，并响应于页写，增加写队列头，并将片段条设置为on 线状态当它满了。

3. 发明授权

US08285946B2 Reducing access contention in flash-based memory systems 有权
标题翻译：减少基于闪存的内存系统中的访问争用
公开(公告)号：US08285946B2
公开(公告)日：2012-10-09
申请号：US12637897
申请日：2009-12-15
申请人： Evangelos S. Eleftheriou , Robert Haas , Peter Mueller , Roman A. Pletka
发明人： Evangelos S. Eleftheriou , Robert Haas , Peter Mueller , Roman A. Pletka
IPC分类号： G06F13/26
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.
摘要翻译：示例性实施例包括一种用于减少基于闪存的存储器系统中的访问争用的方法，该方法包括从具有多个信道的存储器件和多个存储器块中选择处于空闲状态的芯片条带，其中芯片条带包括多个页面，将所述条纹设置为写入状态，为所述多个通道中的每一个设置所述多个通道中的每一个中的写入队列头部，将所述写入队列头部设置到所述第一自由页面中的第一自由页面属于来自芯片条带的信道的芯片，根据写入分配调度器在信道之间分配写请求，产生页写入，并响应于页写，增加写队列头，并将片段条设置为on 线状态当它满了。

4. 发明授权

US08725957B2 Reducing access contention in flash-based memory systems 有权
标题翻译：减少基于闪存的内存系统中的访问争用
公开(公告)号：US08725957B2
公开(公告)日：2014-05-13
申请号：US13563947
申请日：2012-08-01
申请人： Evangelos S. Eleftheriou , Robert Haas , Peter Mueller , Roman A. Pletka
发明人： Evangelos S. Eleftheriou , Robert Haas , Peter Mueller , Roman A. Pletka
IPC分类号： G06F9/52
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.
摘要翻译：示例性实施例包括一种用于减少基于闪存的存储器系统中的访问争用的方法，该方法包括从具有多个信道的存储器件和多个存储器块中选择处于空闲状态的芯片条带，其中芯片条带包括多个页面，将所述条纹设置为写入状态，为所述多个通道中的每一个设置所述多个通道中的每一个中的写入队列头部，将所述写入队列头部设置到所述第一自由页面中的第一自由页面属于来自芯片条带的信道的芯片，根据写入分配调度器在信道之间分配写请求，产生页写入，并响应于页写，增加写队列头，并将片段条设置为on 线状态当它满了。

5. 发明授权

US08700949B2 Reliability scheme using hybrid SSD/HDD replication with log structured management 有权
标题翻译：使用混合SSD / HDD复制与日志结构化管理的可靠性方案
公开(公告)号：US08700949B2
公开(公告)日：2014-04-15
申请号：US13033470
申请日：2011-02-23
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiaoyu Hu , Roman A. Pletka
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiaoyu Hu , Roman A. Pletka
IPC分类号： G06F11/00
CPC分类号： G06F11/2087 , G06F3/0619 , G06F3/065 , G06F3/0679 , G06F3/0688 , G06F11/1435 , G06F11/2056 , G06F11/2069 , G06F11/2089 , G06F12/0246 , G06F2201/85 , G06F2212/7205
摘要： In one embodiment, a method of storing data includes storing a first copy of data in a solid state memory and storing a second copy of the data in a hard disk drive memory substantially simultaneously with the storing the first copy. In another embodiment, a system for storing data includes a solid state memory, at least one hard disk drive memory, and a controller for controlling storage of data in the solid state memory and the hard disk drive memory. Other methods, systems, and computer program products are also described according to various embodiments.
摘要翻译：在一个实施例中，一种存储数据的方法包括将数据的第一副本存储在固态存储器中，并将数据的第二副本与存储第一副本基本上同时存储在硬盘驱动器存储器中。在另一个实施例中，用于存储数据的系统包括固态存储器，至少一个硬盘驱动器存储器和用于控制固态存储器和硬盘驱动器存储器中的数据存储的控制器。根据各种实施例还描述了其它方法，系统和计算机程序产品。

6. 发明授权

US08688914B2 Promotion of partial data segments in flash cache 有权
标题翻译：在Flash缓存中促进部分数据段
公开(公告)号：US08688914B2
公开(公告)日：2014-04-01
申请号：US13286465
申请日：2011-11-01
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Karl A. Nielsen , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Karl A. Nielsen , Roman A. Pletka
IPC分类号： G06F12/00
CPC分类号： G06F3/0619 , G06F3/0646 , G06F3/0688 , G06F12/0246 , G06F12/0253 , G06F12/0811 , G06F12/0862 , G06F12/0864 , G06F12/0871 , G06F12/0897 , G06F12/122 , G06F12/127 , G06F12/128 , G06F2212/1016 , G06F2212/154 , G06F2212/222 , G06F2212/283 , G06F2212/604 , G06F2212/702 , G06F2212/7201
摘要： For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage.
摘要翻译：为了以更有效的方式有效地在二级存储器中运行轨迹，对于与用于控制主存储器中的轨道的定时的顺序位一起使用的时间位，时间位和顺序位从主存储器传送到辅助存储器。时间位允许在辅助存储器上老化。

7. 发明授权

US08688913B2 Management of partial data segments in dual cache systems 有权
标题翻译：双缓存系统中部分数据段的管理
公开(公告)号：US08688913B2
公开(公告)日：2014-04-01
申请号：US13286454
申请日：2011-11-01
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0868 , G06F12/0891 , G06F12/0897 , G06F12/126 , G06F2212/1021 , G06F2212/1041 , G06F2212/222 , G06F2212/283
摘要： For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes.
摘要翻译：为了在由处理器具有较低和较高级别的高速缓存的计算存储环境中移动部分数据段，将包含部分数据段中的一个的整个数据段升级到较低级别和更高级别的高速缓存。整个数据段的请求数据被分割并定位在较高级缓存的降级队列的最近使用（MRU）部分。整个数据段的未请求的数据被分割并定位在较高级别的缓存的降级队列的最近最少使用（LRU）部分。未请求的数据被固定到位，直到整个数据段写入缓存的较低级别完成。

8. 发明申请

US20110246821A1 RELIABILITY SCHEME USING HYBRID SSD/HDD REPLICATION WITH LOG STRUCTURED MANAGEMENT 有权
标题翻译：使用混合SSD / HDD复制与日志结构管理的可靠性方案
公开(公告)号：US20110246821A1
公开(公告)日：2011-10-06
申请号：US13033470
申请日：2011-02-23
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiaoyu Hu , Roman A. Pletka
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiaoyu Hu , Roman A. Pletka
IPC分类号： G06F12/02 , G06F11/14
CPC分类号： G06F11/2087 , G06F3/0619 , G06F3/065 , G06F3/0679 , G06F3/0688 , G06F11/1435 , G06F11/2056 , G06F11/2069 , G06F11/2089 , G06F12/0246 , G06F2201/85 , G06F2212/7205
摘要： In one embodiment, a method of storing data includes storing a first copy of data in a solid state memory and storing a second copy of the data in a hard disk drive memory substantially simultaneously with the storing the first copy. In another embodiment, a system for storing data includes a solid state memory, at least one hard disk drive memory, and a controller for controlling storage of data in the solid state memory and the hard disk drive memory. Other methods, systems, and computer program products are also described according to various embodiments.
摘要翻译：在一个实施例中，一种存储数据的方法包括将数据的第一副本存储在固态存储器中，并将数据的第二副本与存储第一副本基本上同时存储在硬盘驱动器存储器中。在另一个实施例中，用于存储数据的系统包括固态存储器，至少一个硬盘驱动器存储器和用于控制固态存储器和硬盘驱动器存储器中的数据存储的控制器。根据各种实施例还描述了其它方法，系统和计算机程序产品。

9. 发明授权

US09785561B2 Integrating a flash cache into large storage systems 有权
公开(公告)号：US09785561B2
公开(公告)日：2017-10-10
申请号：US12707357
申请日：2010-02-17
申请人： Kevin J. Ash , Michael T. Benhase , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Yu-Cheng Hsu , Xiaoyu Hu , Joseph S. Hyde, II , Roman A. Pletka , Alfred E. Sanchez
发明人： Kevin J. Ash , Michael T. Benhase , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Yu-Cheng Hsu , Xiaoyu Hu , Joseph S. Hyde, II , Roman A. Pletka , Alfred E. Sanchez
IPC分类号： G06F12/00 , G06F12/0866 , G06F13/00 , G06F13/28 , G06F3/06
CPC分类号： G06F12/0866 , G06F3/0611 , G06F3/0655 , G06F3/0685 , G06F2212/214 , G06F2212/2146
摘要： An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.

10. 发明申请

US20130232295A1 ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM 有权
公开(公告)号：US20130232295A1
公开(公告)日：2013-09-05
申请号：US13466861
申请日：2012-05-08
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/126
摘要： Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式