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1. 发明授权

US07250576B2 Chip package having chip extension and method 失效
标题翻译：芯片封装具有芯片扩展和方法
公开(公告)号：US07250576B2
公开(公告)日：2007-07-31
申请号：US10908615
申请日：2005-05-19
申请人： Evan G. Colgan , David L. Edwards , Benjamin V. Fasano , Kamal K. Sikka , Jeffrey A. Zitz , Wei Zou
发明人： Evan G. Colgan , David L. Edwards , Benjamin V. Fasano , Kamal K. Sikka , Jeffrey A. Zitz , Wei Zou
IPC分类号： H05K1/16
CPC分类号： H01L23/04 , H01L23/3675 , H01L23/433 , H01L24/31 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/83051 , H01L2224/83102 , H01L2224/92125 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.
摘要翻译：公开了一种包括用于包含热界面材料（TIM）并提高芯片冷却的芯片延伸的芯片封装以及相关方法。特别地，芯片封装包括芯片，经由TIM耦合到芯片的冷却结构，并且芯片延伸部可热耦合到芯片的外边缘。放置在芯片和冷却结构之间的TIM被芯片延伸部的热循环期间包含，从而可以抑制可在芯片和冷却结构之间移动的芯片边缘处的空隙形成。芯片延伸还通过在冷却结构和芯片之间提供更大的热接触面积，并且如果需要，以比使用具有较低的晶片生产单位输出的较大模具的成本低得多的成本来改善侧向散热。

2. 发明授权

US07518235B2 Method and structure to provide balanced mechanical loading of devices in compressively loaded environments 失效
标题翻译：在压缩负载环境中提供均衡的机械负载装置的方法和结构
公开(公告)号：US07518235B2
公开(公告)日：2009-04-14
申请号：US10906809
申请日：2005-03-08
申请人： Patrick A. Coico , David L. Edwards , Benjamin V. Fasano , Lewis S. Goldmann , Ellyn M. Ingalls , Michael S. June , Hilton T. Toy , Paul A. Zucco
发明人： Patrick A. Coico , David L. Edwards , Benjamin V. Fasano , Lewis S. Goldmann , Ellyn M. Ingalls , Michael S. June , Hilton T. Toy , Paul A. Zucco
IPC分类号： H01L23/34
CPC分类号： H01L23/4006 , H01L2023/405 , H01L2023/4062 , H01L2023/4081 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： An integrated circuit chip mounting structure includes a chip carrier electrically connected to a circuit board with an integrated circuit chip mounted on the chip carrier. In addition, a thermally conductive device is thermally connected to the chip and a set of compressible support members are provided to transmit a portion of an applied compressive load from the thermally conductive device to the chip and chip carrier.
摘要翻译：集成电路芯片安装结构包括芯片载体，其电连接到具有安装在芯片载体上的集成电路芯片的电路板。此外，导热装置热连接到芯片，并且提供一组可压缩支撑构件以将施加的压缩载荷的一部分从导热装置传递到芯片和芯片载体。

3. 发明申请

US20110044369A1 SILICON CARRIER OPTOELECTRONIC PACKAGING 有权
标题翻译：硅载体光电包装
公开(公告)号：US20110044369A1
公开(公告)日：2011-02-24
申请号：US12544696
申请日：2009-08-20
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
IPC分类号： H01S5/18 , H01L31/0232 , H01L23/34 , H01L21/50
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

4. 发明授权

US06436332B1 Low loss glass ceramic composition with modifiable dielectric constant 失效
标题翻译：具有可变介电常数的低损耗玻璃陶瓷组合物
公开(公告)号：US06436332B1
公开(公告)日：2002-08-20
申请号：US09705139
申请日：2000-11-02
申请人： Benjamin V. Fasano , Robert A. Rita
发明人： Benjamin V. Fasano , Robert A. Rita
IPC分类号： C04B35195
CPC分类号： C03C14/004 , C03C2214/08 , C03C2214/20 , H05K1/0306 , Y10T428/24926
摘要： The dielectric constant of low loss tangent glass-ceramic compositions, such as cordierite-based glass ceramics, is modified over a range by selective addition of high dielectric constant ceramics, such as titanates, tantalates and carbides and metals, such as copper. The low loss tangent is retained or improved over a range of frequencies, and the low CTE of the glass-ceramic is maintained. BaTiO3, SrTiO3 and Ta2O5 produce the most effective results.
摘要翻译：通过选择性地添加高介电常数陶瓷，例如钛酸盐，钽酸盐，碳化物和金属如铜，可以在一定范围内改变低损耗相切玻璃 - 陶瓷组合物的介电常数，例如堇青石系玻璃陶瓷。在一定范围的频率范围内保持或改善低损耗角正切，保持玻璃陶瓷的低CTE。 BaTiO3，SrTiO3和Ta2O5产生最有效的结果。

5. 发明授权

US06354844B1 Land grid array alignment and engagement design 失效
标题翻译：土地格栅阵列对齐和接合设计
公开(公告)号：US06354844B1
公开(公告)日：2002-03-12
申请号：US09459552
申请日：1999-12-13
申请人： Patrick A. Coico , Benjamin V. Fasano
发明人： Patrick A. Coico , Benjamin V. Fasano
IPC分类号： H01R1200
CPC分类号： H05K3/325 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/16152 , H01R12/52 , H05K3/303 , H01L2224/0401
摘要： A Land Grid Array electronic package having an array of contact pads is connected to a corresponding array of contact pads on a circuit board through a matching array of conductive pins of a flexible interposer. Alignment of the electronic package to the flexible interposer and flexible interposer to the circuit board is obtained by registration of alignment components to the contact pads and conductive pins. A pair of alignment components, such as pin-like alignment structures, on selected pads of both the electronic package and circuit board mate within alignment holes at the sites of corresponding pin locations in said flexible interposer. Alternatively, the pin-like alignment structures on the electronic package can be extended to pass through the said alignment holes of said flexible interposer into alignment holes which replace the pin-like alignment structure on said circuit board.
摘要翻译：具有接触焊盘阵列的焊盘阵列电子封装通过柔性插入器的导电引脚的匹配阵列连接到电路板上的相应的接触焊盘阵列。通过将对准部件配准到接触焊盘和导电销来获得电子封装与柔性插入件和柔性插入件到电路板的对准。在电子封装和电路板的选定焊盘上的一对对准部件，例如针状对准结构，在所述柔性插入器中的相应引脚位置的位置处的对准孔内匹配。或者，可以将电子封装上的针状对准结构延伸穿过所述柔性插入件的所述对准孔，以对准替代所述电路板上的针状对准结构的对准孔。

6. 发明授权

US06187418B1 Multilayer ceramic substrate with anchored pad 有权
标题翻译：多层陶瓷基板，带锚定垫
公开(公告)号：US06187418B1
公开(公告)日：2001-02-13
申请号：US09356944
申请日：1999-07-19
申请人： Benjamin V. Fasano , David H. Gabriels , Richard F. Indyk , Sundar M. Kamath , Scott I. Langenthal , Srinivasa S. N. Reddy , Rao V. Vallabhaneni
发明人： Benjamin V. Fasano , David H. Gabriels , Richard F. Indyk , Sundar M. Kamath , Scott I. Langenthal , Srinivasa S. N. Reddy , Rao V. Vallabhaneni
IPC分类号： B32B300
CPC分类号： H05K3/4092 , H05K1/0306 , H05K1/113 , H05K3/4053 , H05K3/4611 , H05K3/4629 , H05K2201/09781 , H05K2201/0979 , Y10T428/24917 , Y10T428/24926
摘要： Disclosed is a multilayer ceramic substrate having an outer pad, for example an I/O pad, which is anchored to an inner pad of the multilayer ceramic substrate by either a plurality of vias or one large via. The outer pad and vias are made of high metal material, preferably 100% metal, so they won't adhere very well to the ceramic substrate. The inner pad is a composite metal/ceramic material which will bond very well to the ceramic substrate.
摘要翻译：公开了一种多层陶瓷基板，其具有外焊盘，例如I / O焊盘，其通过多个通孔或一个大通孔锚定到多层陶瓷基板的内焊盘。外垫和通孔由高金属材料制成，优选为100％金属，因此它们将不能很好地粘附到陶瓷基片上。内垫是复合金属/陶瓷材料，其将很好地结合到陶瓷基底上。

7. 发明授权

US5552232A Aluminum nitride body having graded metallurgy 失效
公开(公告)号：US5552232A
公开(公告)日：1996-09-03
申请号：US361351
申请日：1994-12-21
申请人： Jon A. Casey , Carla N. Cordero , Benjamin V. Fasano , David B. Goland , Robert Hannon , Jonathan H. Harris , Lester W. Herron , Gregory M. Johnson , Niranjan M. Patel , Andrew M. Reitter , Subhash L. Shinde , Rao V. Vallabhaneni , Robert A. Youngman
发明人： Jon A. Casey , Carla N. Cordero , Benjamin V. Fasano , David B. Goland , Robert Hannon , Jonathan H. Harris , Lester W. Herron , Gregory M. Johnson , Niranjan M. Patel , Andrew M. Reitter , Subhash L. Shinde , Rao V. Vallabhaneni , Robert A. Youngman
IPC分类号： B32B18/00 , B22F7/02 , C04B35/581 , C04B37/02 , C04B41/51 , C04B41/52 , C04B41/88 , C04B41/89 , C22C29/16 , H01L21/48 , H01L23/373 , H05K1/03 , H05K3/24 , H05K3/40 , H05K3/46 , B22F3/00
CPC分类号： C04B41/009 , B22F7/02 , C04B41/5133 , C04B41/52 , C04B41/88 , C04B41/89 , C22C29/16 , H01L21/4846 , H01L21/486 , H01L23/3731 , H05K3/4061 , B22F2998/00 , C04B2111/00405 , C04B2111/00844 , H01L2924/0002 , H05K1/0306 , H05K2201/035 , H05K2201/09981 , H05K3/248 , H05K3/4611 , H05K3/4629 , Y10S428/901 , Y10T428/12021 , Y10T428/12028 , Y10T428/12056 , Y10T428/31678
摘要： Disclosed is an aluminum nitride body having graded metallurgy and a method for making such a body. The aluminum nitride body has at least one via and includes a first layer in direct contact with the aluminum nitride body and a second layer in direct contact with, and that completely encapsulates, the first layer. The first layer includes 30 to 60 volume percent aluminum nitride and 40 to 70 volume percent tungsten and/or molybdenum while the second layer includes 90 to 100 volume percent of tungsten and/or molybdenum and 0 to 10 volume percent of aluminum nitride.

8. 发明授权

US08559474B2 Silicon carrier optoelectronic packaging 有权
标题翻译：硅载光子包装
公开(公告)号：US08559474B2
公开(公告)日：2013-10-15
申请号：US13604341
申请日：2012-09-05
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank F. Libsch , Sylvain Ouimet , Chrirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank F. Libsch , Sylvain Ouimet , Chrirag S. Patel
IPC分类号： H01S5/024 , H01S5/18 , H01L23/28 , H01L23/18
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

9. 发明申请

US20130233598A1 FLEXIBLE FILM CARRIER TO INCREASE INTERCONNECT DENSITY OF MODULES AND METHODS THEREOF 审中-公开
公开(公告)号：US20130233598A1
公开(公告)日：2013-09-12
申请号：US13414743
申请日：2012-03-08
申请人： Benjamin V. Fasano
发明人： Benjamin V. Fasano
IPC分类号： H05K1/00 , H05K3/30
CPC分类号： H05K3/40 , H01L23/49838 , H01L23/4985 , H01L2924/0002 , H05K1/118 , H05K3/3436 , Y10T29/49139 , Y10T29/49147 , H01L2924/00
摘要： A flexible film carrier and methods of manufacture, and more particularly, methods and structures to increase interconnect density of modules onto circuit boards is discloses. The structure includes a substrate comprising a plurality of holes and a plurality of contacts having a pitch corresponding to a pitch of I/O connections of a laminate. The structure further includes at least one type of connection provided on the substrate and which is positioned so as to avoid interference with a connection of the laminate to a circuit board. The structure further includes wiring electrically connecting the plurality of contacts to the at least one type of connection.

10. 发明授权

US08290008B2 Silicon carrier optoelectronic packaging 有权
标题翻译：硅载光子包装
公开(公告)号：US08290008B2
公开(公告)日：2012-10-16
申请号：US12544696
申请日：2009-08-20
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
IPC分类号： H01S5/022 , H01S5/024
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

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