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1. 发明授权

US08614125B2 Nonvolatile memory devices and methods of forming the same 有权
公开(公告)号：US08614125B2
公开(公告)日：2013-12-24
申请号：US12070219
申请日：2008-02-15
申请人： Eun-Kyung Yim , In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jin-Shi Zhao
发明人： Eun-Kyung Yim , In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jin-Shi Zhao
IPC分类号： H01L29/788
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.

2. 发明申请

US20080197336A1 Nonvolatile memory devices and methods of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20080197336A1
公开(公告)日：2008-08-21
申请号：US12070219
申请日：2008-02-15
申请人： Eun-Kyung Yim , In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jin-Shi Zhao
发明人： Eun-Kyung Yim , In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jin-Shi Zhao
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.
摘要翻译：非易失性存储器件包括半导体衬底上的底电极，底电极上的数据存储层，包含过渡金属氧化物的数据存储层以及设置在数据的顶表面和/或底表面上的开关层存储层，其中包含在所述开关层中的材料的键能和氧比所述过渡金属氧化物和氧中的过渡金属的键能大。

3. 发明申请

US20080062740A1 Methods of programming a resistive memory device 审中-公开
标题翻译：编程电阻式存储器件的方法
公开(公告)号：US20080062740A1
公开(公告)日：2008-03-13
申请号：US11895371
申请日：2007-08-24
申请人： In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jun-Ho Jeong , Eun-Kyung Yim
发明人： In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jun-Ho Jeong , Eun-Kyung Yim
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/0078 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , G11C2213/34
摘要： Methods of programming a RRAM device are provided. An increasing set current is applied to a data storing layer pattern of the RRAM device while measuring a resistance of the data storing layer pattern until the resistance indicates a set state in the data storing layer pattern. An increasing reset voltage is applied to the data storing layer pattern of the RRAM device while measuring the resistance of the data storing layer pattern until the resistance indicates a reset state in the data storing layer pattern.
摘要翻译：提供了编程RRAM设备的方法。在测量数据存储层图案的电阻直到电阻指示数据存储层图案中的设置状态之前，将增加的设置电流应用于RRAM设备的数据存储层图案。在测量数据存储层图案的电阻直到电阻指示数据存储层图案中的复位状态时，将增加的复位电压施加到RRAM器件的数据存储层图案。

4. 发明申请

US20090135642A1 RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS OPERATING RESPONSIVE TO READ OPERATIONS 有权
标题翻译：包括选择的参考存储器电容的电阻存储器件操作响应于读操作
公开(公告)号：US20090135642A1
公开(公告)日：2009-05-28
申请号：US12358936
申请日：2009-01-23
申请人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
发明人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0054 , G11C2213/32 , G11C2213/79
摘要： A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
摘要翻译：基于电阻的随机存取存储器（ReRAM）可以包括读出放大器电路，其响应于对第二块的读取操作，包括耦合到ReRAM的第一块中的参考单元的位线的第一输入。

5. 发明申请

US20090067216A1 RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS 失效
标题翻译：包括选择的参考存储器单元的电阻存储器件
公开(公告)号：US20090067216A1
公开(公告)日：2009-03-12
申请号：US12265941
申请日：2008-11-06
申请人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
发明人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC分类号： G11C11/00 , G11C11/02 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1673
摘要： A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.
摘要翻译：磁存储单元阵列器件可以包括在多个第一和第二存储器单元之间延伸的第一电流源线，该第一和第二存储器单元被配置用于相应的同时编程，并且被配置为进行用于写入多个第一和第二存储器单元之一的足够的编程电流，第一电流源极晶体管，耦合到第一电流源线和字线，编程导体，其耦合到第一电流源晶体管并且延伸跨越耦合到多个第一和第二存储器单元中的一个的位线，被配置为导通编程电流耦合到编程导体并被配置为将编程电流从编程导体切换到第二电流源晶体管输出的第二电流源晶体管，与多个第一和第二晶体管中的一个相邻延伸的第二电流源极线与第一电流源线相对的存储单元，af 第一偏置电路，被配置为将第一偏置电压施加到在读取操作期间被选择访问的第一或第二存储器单元;以及第二偏置电路，被配置为将第二偏置电压施加到未被选择以在读取期间访问的第一或第二存储器单元操作。

6. 发明申请

US20090020745A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRANSITION METAL OXIDE LAYER AND RELATED DEVICE 有权
标题翻译：具有过渡金属氧化物层的半导体器件的制造方法及相关器件
公开(公告)号：US20090020745A1
公开(公告)日：2009-01-22
申请号：US12175602
申请日：2008-07-18
申请人： Jun-Ho Jeong , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , In-Gyu Baek
发明人： Jun-Ho Jeong , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , In-Gyu Baek
IPC分类号： H01L21/329 , H01L47/00
CPC分类号： H01L27/24 , G11C13/003 , G11C2213/76 , H01L27/224
摘要： Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer.
摘要翻译：提供一种具有能够防止蛇电流的开关装置的半导体器件的制造方法。首先，将过渡金属氧化物层和泄漏控制层交替层叠在基板上1〜20次，以形成可变电阻层。与其稳定状态相比，过渡金属氧化物层形成为含有过量的过渡金属。泄漏控制层可以由选自Mg层，Ta层，Al层，Zr层，Hf层，多晶硅层，导电性碳基层和Nb层中的一种形成。

7. 发明申请

US20070103964A1 Resistive memory devices including selected reference memory cells and methods of operating the same 审中-公开
标题翻译：电阻式存储器件包括所选择的参考存储单元及其操作方法
公开(公告)号：US20070103964A1
公开(公告)日：2007-05-10
申请号：US11580766
申请日：2006-10-13
申请人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
发明人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1673
摘要： A method of accessing a resistive memory device can include applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line, A programming current can be conducted via a pair of opposing current source transistors located on first and second opposing sides of the first block to provide the programming current from the first end to the second end across bit lines coupled to resistive memory cells in the first block and to provide the programming current parallel to the second block.
摘要翻译：访问电阻式存储器件的方法可以包括在耦合到第二字线的第二电阻存储器单元块的读取操作期间将预定电压电平施加到耦合到第一电阻存储器单元块的第一字线。编程电流可以位于第一块的第一和第二相对侧上的一对相对的电流源晶体管导通，以提供编程电流，从而从第一端到第二端跨越与第一块中的电阻式存储单元耦合的位线，并提供编程电流平行于第二块。

8. 发明申请

US20110310657A1 RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS OPERATING RESPONSIVE TO READ OPERATIONS 有权
标题翻译：包括选择的参考存储器电容的电阻存储器件操作响应于读操作
公开(公告)号：US20110310657A1
公开(公告)日：2011-12-22
申请号：US13219582
申请日：2011-08-26
申请人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
发明人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0054 , G11C2213/32 , G11C2213/79
摘要： A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
摘要翻译：基于电阻的随机存取存储器（ReRAM）可以包括读出放大器电路，其响应于对第二块的读取操作，包括耦合到ReRAM的第一块中的参考单元的位线的第一输入。

9. 发明授权

US08023311B2 Resistive memory devices including selected reference memory cells operating responsive to read operations 有权
标题翻译：电阻式存储器件包括响应于读取操作而工作的选择的参考存储器单元
公开(公告)号：US08023311B2
公开(公告)日：2011-09-20
申请号：US12358936
申请日：2009-01-23
申请人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
发明人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0054 , G11C2213/32 , G11C2213/79
摘要： A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
摘要翻译：基于电阻的随机存取存储器（ReRAM）可以包括读出放大器电路，其响应于对第二块的读取操作，包括耦合到ReRAM的第一块中的参考单元的位线的第一输入。

10. 发明授权

US07952914B2 Memory devices including multi-bit memory cells having magnetic and resistive memory elements and related methods 失效
标题翻译：存储器件包括具有磁性和电阻存储元件的多位存储单元和相关方法
公开(公告)号：US07952914B2
公开(公告)日：2011-05-31
申请号：US11804327
申请日：2007-05-17
申请人： In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jun-Ho Jeong
发明人： In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jun-Ho Jeong
IPC分类号： G11C11/00
CPC分类号： G11C11/15 , G11C11/005 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/5607 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/02 , H01L27/224 , H01L27/228 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/147 , Y10S977/754 , Y10S977/935
摘要： An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.
摘要翻译：集成电路存储器件可以包括集成电路衬底和集成电路衬底上的多位存储单元。多位存储器单元可以被配置为通过改变多位存储单元的第一特性来存储第一位数据，并且通过改变多位存储单元的第二特性来存储第二位数据。此外，第一和第二特征可以不同。还讨论了相关方法。

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