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1. 发明授权

US07897463B2 Methods of fabricating vertical twin-channel transistors 失效
标题翻译：制造垂直双通道晶体管的方法
公开(公告)号：US07897463B2
公开(公告)日：2011-03-01
申请号：US12651688
申请日：2010-01-04
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/513 , H01L29/66666 , H01L29/7831
摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
摘要翻译：晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。栅电极设置在第一和第二栅极绝缘体之间。第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

2. 发明申请

US20100105181A1 METHODS OF FABRICATING VERTICAL TWIN-CHANNEL TRANSISTORS 失效
标题翻译：制作垂直双通道晶体管的方法
公开(公告)号：US20100105181A1
公开(公告)日：2010-04-29
申请号：US12651688
申请日：2010-01-04
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/513 , H01L29/66666 , H01L29/7831
摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
摘要翻译：晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。栅电极设置在第一和第二栅极绝缘体之间。第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

3. 发明申请

US20080029811A1 Vertical Twin-Channel Transistors and Methods of Fabricating the Same 审中-公开
标题翻译：垂直双通道晶体管及其制造方法
公开(公告)号：US20080029811A1
公开(公告)日：2008-02-07
申请号：US11687079
申请日：2007-03-16
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/513 , H01L29/66666 , H01L29/7831
摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
摘要翻译：晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。栅电极设置在第一和第二栅极绝缘体之间。第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

4. 发明申请

US20060289907A1 Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions and methods of fabricating the same 失效
标题翻译：具有低于源区和漏区的缓冲区的金属氧化物半导体（MOS）晶体管及其制造方法
公开(公告)号：US20060289907A1
公开(公告)日：2006-12-28
申请号：US11513474
申请日：2006-08-31
申请人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
发明人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/66651 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/0653
摘要： A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
摘要翻译：在集成电路基板上设置有集成电路基板和MOS晶体管的金属氧化物半导体（MOS）晶体管的单位电池。 MOS晶体管具有源极区，漏极区和栅极。栅极在源极区域和漏极区域之间。第一和第二间隔开的缓冲区设置在源极区域和漏极区域之间以及源区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

5. 发明授权

US07541645B2 Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions 失效
标题翻译：金属氧化物半导体（MOS）晶体管具有低于源极和漏极区域的缓冲区域
公开(公告)号：US07541645B2
公开(公告)日：2009-06-02
申请号：US11513474
申请日：2006-08-31
申请人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
发明人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
IPC分类号： H01L29/76
CPC分类号： H01L29/66651 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/0653
摘要： A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
摘要翻译：在集成电路基板上设置有集成电路基板和MOS晶体管的金属氧化物半导体（MOS）晶体管的单位电池。 MOS晶体管具有源极区，漏极区和栅极。栅极在源极区域和漏极区域之间。第一和第二间隔开的缓冲区设置在源极区域和漏极区域之间以及源区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

6. 发明申请

US20080001218A1 Metal Oxide Semiconductor (MOS) Transistors Having Three Dimensional Channels 有权
标题翻译：具有三维通道的金属氧化物半导体（MOS）晶体管
公开(公告)号：US20080001218A1
公开(公告)日：2008-01-03
申请号：US11854734
申请日：2007-09-13
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

7. 发明授权

US07285466B2 Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
标题翻译：形成具有三维通道的金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US07285466B2
公开(公告)日：2007-10-23
申请号：US10909471
申请日：2004-08-02
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

8. 发明申请

US20050032322A1 Metal oxide semiconductor (MOS) transistors having three dimensional channels and methods of fabricating the same 有权
标题翻译：具有三维通道的金属氧化物半导体（MOS）晶体管及其制造方法
公开(公告)号：US20050032322A1
公开(公告)日：2005-02-10
申请号：US10909471
申请日：2004-08-02
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L29/786 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/76 , H01L21/3205
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

9. 发明授权

US07473963B2 Metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
标题翻译：具有三维通道的金属氧化物半导体（MOS）晶体管
公开(公告)号：US07473963B2
公开(公告)日：2009-01-06
申请号：US11854734
申请日：2007-09-13
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

10. 发明授权

US07122431B2 Methods of fabrication metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions 有权
标题翻译：制造具有低于源极和漏极区域的缓冲区的金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US07122431B2
公开(公告)日：2006-10-17
申请号：US10754676
申请日：2004-01-09
申请人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
发明人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/00 , H01L21/20 , H01L21/425
CPC分类号： H01L29/66651 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/0653
摘要： Methods of forming a unit cell of a metal oxide semiconductor (MOS) transistor are provided. An integrated circuit substrate is formed. A MOS transistor is formed on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. The first and second spaced apart buffer regions are formed beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
摘要翻译：提供了形成金属氧化物半导体（MOS）晶体管的晶胞的方法。形成集成电路基板。在集成电路基板上形成MOS晶体管。 MOS晶体管具有源极区，漏极区和栅极。栅极在源极区域和漏极区域之间。第一和第二间隔开的缓冲区形成在源极区域和漏极区域之间以及源极区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

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