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1. 发明授权

US07487473B2 Enabling netlist for modeling of technology dependent BEOL process variation 失效
标题翻译：启用基于技术的BEOL过程变化建模网络表
公开(公告)号：US07487473B2
公开(公告)日：2009-02-03
申请号：US11531023
申请日：2006-09-12
申请人： Essam Mina , William Piper , Wayne H. Woods, Jr.
发明人： Essam Mina , William Piper , Wayne H. Woods, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10
摘要： A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one embodiment, the method includes obtaining a netlist of electrical elements (i.e., BEOL parasitic resistance and/or capacitance), the netlist including estimated electrical values for the electrical elements and geometric data for at least one of the electrical elements; determining variations of the electrical value for a selected electrical element based on the geometric data using a scaling methodology; and placing a model call in the netlist, the model call implementing the variations of electrical value for the selected electrical element. The revised netlist can be used to model the IC design and includes a scaling of electrical values without having to generate more than one netlist.
摘要翻译：公开了一种方法，系统和程序产品，其实现了用于对技术依赖的后端（BEOL）过程变化的建模的集成电路（IC）设计的网表。在一个实施例中，该方法包括获得电气元件的网表（即，BEOL寄生电阻和/或电容），所述网表包括电元件的估计电值和至少一个电气元件的几何数据; 基于使用缩放方法的几何数据确定所选择的电气元件的电气值的变化; 并将模型呼叫放置在网表中，模型呼叫实现所选择的电气元件的电气值的变化。经修订的网表可用于对IC设计进行建模，并包括电气值的缩放，而不必生成多个网表。

2. 发明授权

US07490304B2 Determining geometrical configuration of interconnect structure 失效
标题翻译：确定互连结构的几何结构
公开(公告)号：US07490304B2
公开(公告)日：2009-02-10
申请号：US11426053
申请日：2006-06-23
申请人： Essam Mina , William Piper , Wayne H. Woods, Jr.
发明人： Essam Mina , William Piper , Wayne H. Woods, Jr.
IPC分类号： G06F17/50
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method includes obtaining simulation data correlating capacitance data, resistance data and geometrical configuration data for a plurality of interconnect structures having different geometrical configurations; measuring a capacitance value and a resistance value from the interconnect structure of the test structure; and determining the geometrical configuration of the interconnect structure by comparing the capacitance value and the resistance value to the simulation data.
摘要翻译：公开了用于确定测试结构的互连结构的几何结构而不进行横截面或光学测量的方法。在一个实施例中，该方法包括获得关于具有不同几何构造的多个互连结构的电容数据，电阻数据和几何配置数据相关联的模拟数据; 从测试结构的互连结构测量电容值和电阻值; 以及通过将电容值和电阻值与仿真数据进行比较来确定互连结构的几何结构。

3. 发明申请

US20070298527A1 DETERMINING GEOMETRICAL CONFIGURATION OF INTERCONNECT STRUCTURE 失效
标题翻译：确定互连结构的几何配置
公开(公告)号：US20070298527A1
公开(公告)日：2007-12-27
申请号：US11426053
申请日：2006-06-23
申请人： Essam Mina , William Piper , Wayne H. Woods
发明人： Essam Mina , William Piper , Wayne H. Woods
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method includes obtaining simulation data correlating capacitance data, resistance data and geometrical configuration data for a plurality of interconnect structures having different geometrical configurations; measuring a capacitance value and a resistance value from the interconnect structure of the test structure; and determining the geometrical configuration of the interconnect structure by comparing the capacitance value and the resistance value to the simulation data.
摘要翻译：公开了用于确定测试结构的互连结构的几何结构而不进行横截面或光学测量的方法。在一个实施例中，该方法包括获得关于具有不同几何构造的多个互连结构的电容数据，电阻数据和几何配置数据相关联的模拟数据; 从测试结构的互连结构测量电容值和电阻值; 以及通过将电容值和电阻值与仿真数据进行比较来确定互连结构的几何结构。

4. 发明申请

US20080066024A1 ENABLING NETLIST FOR MODELING OF TECHNOLOGY DEPENDENT BEOL PROCESS VARIATION 失效
标题翻译：用于建立技术依赖性波束过程变化的启发网络列表
公开(公告)号：US20080066024A1
公开(公告)日：2008-03-13
申请号：US11531023
申请日：2006-09-12
申请人： Essam Mina , William Piper , Wayne H. Woods
发明人： Essam Mina , William Piper , Wayne H. Woods
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10
摘要： A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one embodiment, the method includes obtaining a netlist of electrical elements (i.e., BEOL parasitic resistance and/or capacitance), the netlist including estimated electrical values for the electrical elements and geometric data for at least one of the electrical elements; determining variations of the electrical value for a selected electrical element based on the geometric data using a scaling methodology; and placing a model call in the netlist, the model call implementing the variations of electrical value for the selected electrical element. The revised netlist can be used to model the IC design and includes a scaling of electrical values without having to generate more than one netlist.
摘要翻译：公开了一种方法，系统和程序产品，其实现了用于对技术依赖的后端（BEOL）过程变化的建模的集成电路（IC）设计的网表。在一个实施例中，该方法包括获得电气元件的网表（即，BEOL寄生电阻和/或电容），所述网表包括电元件的估计电值和至少一个电气元件的几何数据; 基于使用缩放方法的几何数据确定所选择的电气元件的电气值的变化; 并将模型呼叫放置在网表中，模型呼叫实现所选择的电气元件的电气值的变化。经修订的网表可用于对IC设计进行建模，并包括电气值的缩放，而不必生成多个网表。

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