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1. 发明授权

US5367183A Semiconductor device with complementary transistors 失效
标题翻译：具有互补晶体管的半导体器件
公开(公告)号：US5367183A
公开(公告)日：1994-11-22
申请号：US43558
申请日：1993-04-07
申请人： Ernesto Perea , Daniel Delagebeaudeuf
发明人： Ernesto Perea , Daniel Delagebeaudeuf
IPC分类号： H01L21/8232 , H01L27/06 , H01L27/095 , H01L29/36 , H01L29/778 , H01L29/80 , H01L29/205
CPC分类号： H01L29/7786 , H01L27/0605 , H01L29/365
摘要： Disclosed is a system with at least two complementary transistors, having n and p channels but comprising a heterostructure of junctions between III-V group materials. In order to balance the threshold voltages in the two channels, namely the n (2DEG) and p (2DHG) channels, at least two p and n delta doped layers are included in two layers of the heterostructure, at levels included between the channels (2DEG, 2DHG) and the gate electrodes. The n delta doped layer is then removed by localized etching right above the p channel transistor. Application to fast logic circuits.
摘要翻译：公开了具有至少两个互补晶体管的系统，其具有n沟道和p沟道，但是包含III-V族材料之间的结的异质结构。为了平衡两个通道中的阈值电压，即n（2DEG）和p（2DHG）通道，至少两个p和n delta掺杂层包含在异质结构的两层中， 2DEG，2DHG）和栅电极。然后通过在p沟道晶体管正上方的局部蚀刻去除n-Δ掺杂层。应用于快速逻辑电路。

2. 发明授权

US4568843A Bistable logic device, operating from DC to 10 GHz, and frequency divider including this bistable device 失效
标题翻译：双稳态逻辑器件，工作在直流到10 GHz，分频器包括双稳态器件
公开(公告)号：US4568843A
公开(公告)日：1986-02-04
申请号：US505175
申请日：1983-06-17
申请人： Maurice Gloanec , Georges Bert , Ernesto Perea
发明人： Maurice Gloanec , Georges Bert , Ernesto Perea
IPC分类号： H03K3/037 , H03K3/356 , H03K3/289 , H03K3/288
CPC分类号： H03K3/037 , H03K3/356069
摘要： A bistable logic device, of the RSTT type, operating up to X band. The bistable logic device is organized into three stages: an input stage of four NOR operators (21, 31, 41, 51), a second stage of two OR operators (61, 71) and an output stage of two OR operators (62, 72). Each NOR operator of the input stage drives in parallel an OR operator of the second stage and an OR operator of the output stage. Each of the four OR operators are fed back to an input of one of the four NOR operators of the input stage. The organization in logic NOR/OR form makes it possible to use faster single gate transistors. The present invention may be particularly useful to frequency dividers for interfacing between signals at GHz frequency and measurement and control circuits at MHz frequency.
摘要翻译： RST和upbar＆T类型的双稳态逻辑器件，可运行到X频段。双稳态逻辑器件分为三个阶段：四个NOR运算符（21,31,41,51）的输入级，两个OR运算符（61,71）的第二级和两个OR运算符的输出级（62， 72）。输入级的每个NOR运算符并行驱动第二级的OR运算符和输出级的OR运算符。四个OR运算符中的每一个被反馈到输入级的四个NOR运算符之一的输入。逻辑NOR / OR形式的组织使得可以使用更快的单栅极晶体管。本发明对于用于在GHz频率的信号与MHz频率的测量和控制电路之间进行接口的分频器可能是特别有用的。

3. 发明授权

US5043607A Output interface circuit between two circuits of different natures 失效
标题翻译：输出接口电路在两个不同性质的电路之间
公开(公告)号：US5043607A
公开(公告)日：1991-08-27
申请号：US540637
申请日：1990-06-19
申请人： Jean-Yves Danckaert , Ernesto Perea
发明人： Jean-Yves Danckaert , Ernesto Perea
IPC分类号： H03K19/0185
CPC分类号： H03K19/018535
摘要： This interface constitutes a matching of the output signals of a first circuit, made of GaAs for example, with the limit values of the input signals of a second digital circuit, made of silicon for example. It has a current amplifier which receives the output signal of the GaAs circuit. The voltages at the high level are controlled by a diode in series with a transistor which is then on. At the low level, the transistor is off, and it is two diodes, in parallel with the transistor, that control the output voltage. This interface is integrated into the chip of the digital circuit, made of GaAs. Single figure.
摘要翻译：该接口构成例如由GaAs制成的第一电路的输出信号与由例如硅制成的第二数字电路的输入信号的极限值的匹配。它具有接收GaAs电路的输出信号的电流放大器。高电平处的电压由与然后导通的晶体管串联的二极管控制。在低电平时，晶体管截止，与控制输出电压的是晶体管并联的两个二极管。该接口集成在由GaAs制成的数字电路芯片中。单身人物

4. 发明授权

US4721985A Variable capacitance element controllable by a D.C. voltage 失效
标题翻译：可变电容元件可由直流电压控制
公开(公告)号：US4721985A
公开(公告)日：1988-01-26
申请号：US750478
申请日：1985-07-01
申请人： Dimitrios Pavlidis , Erhard Kohn , Ernesto Perea , John Magarshack
发明人： Dimitrios Pavlidis , Erhard Kohn , Ernesto Perea , John Magarshack
IPC分类号： H01L29/93 , H01L29/40 , H01L29/20 , H01L29/48
CPC分类号： H01L29/93
摘要： The invention relates to a variable capacitance element operating in the ultra-high frequency range. In order to integrate this element on to an integrated circuit chip, the element is designed so that the control voltage does not interfere with the ultra-high frequency signal and has neither filters nor shock chokes which are not integrable. The element according to the invention utilizes the junction capacitances variation of at least one diode, reverse-biased by a voltage across a resistor, the high frequency signal being at the diode anode. The element construction comprises an active zone in a semiinsulating substrate. Two metallizations partly cover the active zone and form therewith at least one diode. A projection to the active zone forms the resistor, to which is applied the control voltage. The diodes are p-n junctions of schottky diodes. The semiconductor material is Si or from the III-V group. Application to oscillators, filters, phase shifters, etc. in ultra-high frequency equipment.
摘要翻译：本发明涉及在超高频范围内工作的可变电容元件。为了将该元件集成到集成电路芯片上，元件被设计成使得控制电压不干扰超高频信号，并且既不具有滤波器也不具有不可积分的抗冲击电抗器。根据本发明的元件利用由电阻器两端的电压反向偏置的至少一个二极管的结电容变化，高频信号在二极管阳极处。元件结构包括半绝缘衬底中的活性区。两个金属化部分地覆盖有源区并与其形成至少一个二极管。对有源区的投影形成电阻，施加控制电压。二极管是肖特基二极管的p-n结。半导体材料是Si或III-V族。应用于超高频设备中的振荡器，滤波器，移相器等。

5. 发明授权

US06287936B1 Method of forming porous silicon in a silicon substrate, in particular for improving the performance of an inductive circuit 有权
标题翻译：在硅衬底中形成多孔硅的方法，特别是用于改善电感电路的性能
公开(公告)号：US06287936B1
公开(公告)日：2001-09-11
申请号：US09304887
申请日：1999-05-04
申请人： Ernesto Perea , Guillermo Bomchil , Aomar Halimaoui
发明人： Ernesto Perea , Guillermo Bomchil , Aomar Halimaoui
IPC分类号： H01L2176
CPC分类号： H01L28/10 , H01L21/3063 , H01L27/0688 , H01L27/08
摘要： The method is for forming porous silicon in a silicon substrate, in particular for improving the quality factor of an inductive circuit produced on a silicon semiconductor wafer which also incorporates integrated transistors. The rear face of the wafer, already incorporating the transistors and the inductive circuit on its front face, is placed in contact with an acid electrolyte containing hydrofluoric acid and at least one other acid. An anodic oxidation of the silicon of the wafer at the rear face is carried out so as to convert this silicon into porous silicon over a predetermined height from the rear face which is in contact with the electrolyte.
摘要翻译：该方法用于在硅衬底中形成多孔硅，特别是用于改善在还包含集成晶体管的硅半导体晶片上产生的感应电路的品质因数。已经将晶体管和感应电路结合在其前表面上的晶片的后表面与含有氢氟酸和至少一种其它酸的酸性电解液接触。在背面进行晶片的硅的阳极氧化，以便将其从与电解质接触的背面预定的高度转化为多孔硅。

6. 发明授权

US5045727A Interface circuit between two circuits of different logic types 失效
标题翻译：不同逻辑类型的两个电路之间的接口电路
公开(公告)号：US5045727A
公开(公告)日：1991-09-03
申请号：US538703
申请日：1990-06-15
申请人： Jean-Yves Danckaert , Ernesto Perea
发明人： Jean-Yves Danckaert , Ernesto Perea
IPC分类号： H03K19/0185
CPC分类号： H03K19/018535
摘要： This interface constitutes an adaptation of the output signals of a first circuit, made of silicon for example, to the limit values of the input signals in a second digital circuit, made of GaAs for example. It includes a first stage (A) consisting of two parallel-mounted shifters, in which the input signal (E) and a reference (Ref) are shifted. A second stage (B), of the BFL type, compares these two values and a third stage (C) regenerates and amplifies the signals. A fourth stage (D) may give a complementary value. This interface is integrated into the chip of the second digital circuit which is made of GaAs.
摘要翻译：该接口构成例如由例如由硅制成的第一电路的输出信号到例如由GaAs制成的第二数字电路中的输入信号的极限值。它包括由两个并联安装的移位器组成的第一级（A），其中输入信号（E）和参考（Ref）被移位。 BFL型的第二级（B）比较这两个值，第三级（C）再生并放大信号。第四阶段（D）可以给出补充价值。该接口集成在由GaAs制成的第二数字电路的芯片中。

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