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1. 发明授权

US5604455A Transition detection device generating a variable-duration pulse 失效
标题翻译：产生可变持续时间脉冲的转换检测装置
公开(公告)号：US5604455A
公开(公告)日：1997-02-18
申请号：US441734
申请日：1995-05-16
申请人： Thierry Bion , Jean-Yves Danckaert
发明人： Thierry Bion , Jean-Yves Danckaert
IPC分类号： G11C8/18 , H03K7/00 , H03K19/00
CPC分类号： G11C8/18
摘要： A transition detection device, generating a variable-duration pulse, such as an enable signal for the input circuits of a CMOS static memory circuit, receiving an input signal that includes a delay circuit of determined delay value, making it possible to generate a delayed enable signal, with a safety margin of duration equal to the delay value. A calibration circuit is provided, which includes an exclusive-OR circuit receiving the input signal on a first input. A controlled delay circuit is provided to deliver an input signal delayed by a second delay value to a second input of the exclusive-OR circuit, which, upon access by the CEB signal, delivers a calibrated output pulse of duration equal to the second delay value, and truncated pulses for any transition occurring on the other inputs of the circuit, in the presence of address transitions or of other, not strictly simultaneous, inputs.
摘要翻译：一种转换检测装置，生成诸如用于CMOS静态存储器电路的输入电路的使能信号的可变持续时间脉冲，接收包括确定的延迟值的延迟电路的输入信号，使得可以产生延迟使能信号，持续时间的安全余量等于延迟值。提供了一种校准电路，其包括在第一输入端接收输入信号的异或电路。提供受控延迟电路以将延迟了第二延迟值的输入信号传送到异或电路的第二输入，该异或电路在由CEB信号访问时传递等于第二延迟值的持续时间的校准输出脉冲以及在存在地址转换或其他而不是严格同时的输入的情况下，在电路的其他输入端上发生的任何转换的截断脉冲。

2. 发明授权

US5043607A Output interface circuit between two circuits of different natures 失效
标题翻译：输出接口电路在两个不同性质的电路之间
公开(公告)号：US5043607A
公开(公告)日：1991-08-27
申请号：US540637
申请日：1990-06-19
申请人： Jean-Yves Danckaert , Ernesto Perea
发明人： Jean-Yves Danckaert , Ernesto Perea
IPC分类号： H03K19/0185
CPC分类号： H03K19/018535
摘要： This interface constitutes a matching of the output signals of a first circuit, made of GaAs for example, with the limit values of the input signals of a second digital circuit, made of silicon for example. It has a current amplifier which receives the output signal of the GaAs circuit. The voltages at the high level are controlled by a diode in series with a transistor which is then on. At the low level, the transistor is off, and it is two diodes, in parallel with the transistor, that control the output voltage. This interface is integrated into the chip of the digital circuit, made of GaAs. Single figure.
摘要翻译：该接口构成例如由GaAs制成的第一电路的输出信号与由例如硅制成的第二数字电路的输入信号的极限值的匹配。它具有接收GaAs电路的输出信号的电流放大器。高电平处的电压由与然后导通的晶体管串联的二极管控制。在低电平时，晶体管截止，与控制输出电压的是晶体管并联的两个二极管。该接口集成在由GaAs制成的数字电路芯片中。单身人物

3. 发明授权

US5045727A Interface circuit between two circuits of different logic types 失效
标题翻译：不同逻辑类型的两个电路之间的接口电路
公开(公告)号：US5045727A
公开(公告)日：1991-09-03
申请号：US538703
申请日：1990-06-15
申请人： Jean-Yves Danckaert , Ernesto Perea
发明人： Jean-Yves Danckaert , Ernesto Perea
IPC分类号： H03K19/0185
CPC分类号： H03K19/018535
摘要： This interface constitutes an adaptation of the output signals of a first circuit, made of silicon for example, to the limit values of the input signals in a second digital circuit, made of GaAs for example. It includes a first stage (A) consisting of two parallel-mounted shifters, in which the input signal (E) and a reference (Ref) are shifted. A second stage (B), of the BFL type, compares these two values and a third stage (C) regenerates and amplifies the signals. A fourth stage (D) may give a complementary value. This interface is integrated into the chip of the second digital circuit which is made of GaAs.
摘要翻译：该接口构成例如由例如由硅制成的第一电路的输出信号到例如由GaAs制成的第二数字电路中的输入信号的极限值。它包括由两个并联安装的移位器组成的第一级（A），其中输入信号（E）和参考（Ref）被移位。 BFL型的第二级（B）比较这两个值，第三级（C）再生并放大信号。第四阶段（D）可以给出补充价值。该接口集成在由GaAs制成的第二数字电路的芯片中。

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