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1. 发明授权

US07461209B2 Transient cache storage with discard function for disposable data 有权
标题翻译：用于一次性数据的具有丢弃功能的瞬态缓存存储
公开(公告)号：US07461209B2
公开(公告)日：2008-12-02
申请号：US11295300
申请日：2005-12-06
申请人： Erik R. Altman , Michael Karl Gschwind , Robert Kevin Montoye , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik R. Altman , Michael Karl Gschwind , Robert Kevin Montoye , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F12/12
CPC分类号： G06F12/1491 , G06F9/3808 , G06F9/3844 , G06F12/0802 , G06F12/0804 , G06F12/12
摘要： A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.
摘要翻译：公开了一种用于存储非关键处理器信息而不对处理器设计造成重大成本的方法和装置。瞬态数据存储在处理器本地缓存层次结构中。附加控制位构成高速缓存地址的一部分，其中具有控制位置位的地址被指定为“瞬时存储地址”。瞬态存储地址不会被写回外部主存储器，而当从最后一级高速缓存驱逐时，它们将被丢弃。优选地，瞬态存储地址是“特权的”，因为它们不能被软件访问或只能具有具有适当权限的监督或管理员级软件访问。提供了许多管理功能/指令，以允许管理员/管理软件管理和/或修改瞬态缓存存储的行为。这种瞬态存储方案允许高速缓存层级来存储处理器核心可能使用的数据项，但是可能太昂贵以分配给外部存储器。

2. 发明授权

US06970982B2 Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions 失效
标题翻译：通过广播TLB无效输入指令来在多处理器系统中维持一致性的方法和系统
公开(公告)号：US06970982B2
公开(公告)日：2005-11-29
申请号：US10676540
申请日：2003-10-01
申请人： Erik R. Altman , Peter G. Capek , Michael Karl Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
发明人： Erik R. Altman , Peter G. Capek , Michael Karl Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
IPC分类号： G06F12/10 , G06F13/00
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

3. 发明授权

US06779049B2 Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism 有权
标题翻译：具有附加处理单元的对称多处理系统能够访问共享存储器而不在结构上配置地址转换机制
公开(公告)号：US06779049B2
公开(公告)日：2004-08-17
申请号：US09736585
申请日：2000-12-14
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
IPC分类号： G06F1328
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

4. 发明授权

US06907477B2 Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors 失效
标题翻译：使用DMAC的对称多处理系统允许连接的处理器进行地址转换
公开(公告)号：US06907477B2
公开(公告)日：2005-06-14
申请号：US10782044
申请日：2004-02-19
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
IPC分类号： G06F12/10 , G06F13/28 , G06F9/28 , G06F13/368
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：一种用于附接处理单元访问SMT系统中的共享存储器的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

5. 发明授权

US08589662B2 Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals 失效
标题翻译：基于比较预测和实际相关性控制信号来接受或回滚指令的执行
公开(公告)号：US08589662B2
公开(公告)日：2013-11-19
申请号：US13371181
申请日：2012-02-10
申请人： Erik R. Altman , Michael K. Gschwind , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman , Victor V. Zyuban
发明人： Erik R. Altman , Michael K. Gschwind , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman , Victor V. Zyuban
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/3838 , G06F9/3859 , G06F9/3873
摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.
摘要翻译：在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。精确的控制信号矢量缓存可以完成。每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存击中。

6. 发明授权

US07735072B1 Method and apparatus for profiling computer program execution 失效
标题翻译：用于分析计算机程序执行的方法和装置
公开(公告)号：US07735072B1
公开(公告)日：2010-06-08
申请号：US09637078
申请日：2000-08-11
申请人： Erik R. Altman , Kemal Ebcioglu , Michael Karl Gschwind , Sumedh Sathaye
发明人： Erik R. Altman , Kemal Ebcioglu , Michael Karl Gschwind , Sumedh Sathaye
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： According to a first aspect of the invention there is provided a method for profiling computer program executions in a computer processing system having a processor and a memory hierarchy. The method includes the step of executing a computer program. Profile counts are stored in a memory array for events associated with the execution of the computer program. The memory array is separate and distinct from the memory hierarchy so as to not perturb normal operations of the memory hierarchy.
摘要翻译：根据本发明的第一方面，提供了一种用于在具有处理器和存储器层次的计算机处理系统中对计算机程序执行进行分析的方法。该方法包括执行计算机程序的步骤。配置文件计数存储在与执行计算机程序相关的事件的存储器阵列中。存储器阵列与存储器层次结构是分开的，不同于内存层次结构的正常操作。

7. 发明授权

US07487330B2 Method and apparatus for transferring control in a computer system with dynamic compilation capability 失效
标题翻译：用于在具有动态编译能力的计算机系统中传送控制的方法和装置
公开(公告)号：US07487330B2
公开(公告)日：2009-02-03
申请号：US09847776
申请日：2001-05-02
申请人： Erik R. Altman , Kemal Ebcioglu , Michael Karl Gschwind , David Arnold Luick
发明人： Erik R. Altman , Kemal Ebcioglu , Michael Karl Gschwind , David Arnold Luick
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/45516
摘要： In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the instruction is disclosed. The system and method include the setting of a tag for entry points of each instruction in a first representation that has been translated to a second representation. The tag is stored in memory in association with each such instruction. When a given instruction in a first representation is to be executed, the tag is examined, and if it indicates that a translated version of the instruction has previously been generated, control is passed to execution of the instruction in the second representation. The second representation can be a different instruction set representation, or an optimized representation in the same instruction set as the original instruction.
摘要翻译：在动态编译计算机系统中，公开了一种用于将控制从第一表示中的指令的执行有效地传送到指令的第二表示的系统和方法。该系统和方法包括在已被翻译为第二表示的第一表示中设置每个指令的入口点的标签。标签与每个这样的指令相关联地存储在存储器中。当要执行第一表示中的给定指令时，检查标签，并且如果其指示已经生成了指令的转换版本，则将控制传递给第二表示中的指令的执行。第二表示可以是与原始指令相同的指令集中的不同指令集表示或优化表示。

8. 发明授权

US07206923B2 Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling 有权
标题翻译：无需注册分配，分配，溢出和重新填充的方法和设备
公开(公告)号：US07206923B2
公开(公告)日：2007-04-17
申请号：US10735054
申请日：2003-12-12
申请人： Alexandre E. Eichenberger , Erik R. Altman , Sumedh W. Sathaye , John-David Wellman
发明人： Alexandre E. Eichenberger , Erik R. Altman , Sumedh W. Sathaye , John-David Wellman
IPC分类号： G06F12/00 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30134 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A method and apparatus is provided to manage data in computer registers in a program, making more computer registers available to one or more programmers utilizing a name level instruction. The method and apparatus disclosed herein presents a way of reducing the overhead of register management, by introducing a concept of a name level for each of the named architected registers in a processor. The method provides a programmer with a larger register name-space while not increasing the size of the instruction word in the processor instruction-set architecture. It also provides for the facilitation of architectural features which overload the architected register namespace and ease the overhead of register management. This provides for the addition of more computer registers without changing the instruction format of the computer.
摘要翻译：提供了一种方法和装置来管理程序中的计算机寄存器中的数据，使得使用名称级别指令的一个或多个程序员可以使用更多的计算机寄存器。本文公开的方法和装置通过在处理器中引入每个命名架构寄存器的名称级别的概念来呈现减少注册管理开销的方式。该方法为编程器提供了更大的寄存器名称空间，而不增加处理器指令集架构中的指令字的大小。它还提供了对架构特征的便利化，这样就可以使架构化的寄存器命名空间过载，并且简化了寄存器管理的开销。这样可以增加更多的计算机寄存器，而不用改变计算机的指令格式。

9. 发明授权

US06704855B1 Method and apparatus for reducing encoding needs and ports to shared resources in a processor 失效
标题翻译：用于将编码需求和端口减少到处理器中的共享资源的方法和装置
公开(公告)号：US06704855B1
公开(公告)日：2004-03-09
申请号：US09585766
申请日：2000-06-02
申请人： Erik R. Altman , Jaime H. Moreno , Mayan Moudgill
发明人： Erik R. Altman , Jaime H. Moreno , Mayan Moudgill
IPC分类号： G06F930
CPC分类号： G06F9/30098 , G06F9/30141 , G06F9/3016 , G06F9/3824 , G06F9/3853
摘要： The present invention relates to a method for accessing elements from a shared resource to be used by consumers that perform actions according to corresponding operations. The method creates a packet of operations to be processed simultaneously, wherein the elements from the shared resource used by the operations are specified by source and destination identifier fields that are shared among the operations in such a way that the sum of all the elements from the shared resource used by the operations does not exceed a total number of identifiers available in the packet. The method also reads the elements from the shared resource according to the shared identifier fields specified in the packet. The method decodes a number of elements from the shared resource needed by each operation, by passing the operations to an operation decoder having a defined routing scheme based on the needs of the operations. The method also routes the elements to the consumers performing operations and resulting values to the shared resource, according to a routing signal of the operation decoder.
摘要翻译：本发明涉及一种从共享资源访问要由使用者根据相应操作执行动作的消费者的方法。该方法创建要同时处理的一组操作，其中由操作使用的来自共享资源的元素由在操作之间共享的源和目标标识符字段指定，使得来自操作使用的共享资源不会超过数据包中可用的标识符的总数。该方法还根据分组中指定的共享标识符字段从共享资源中读取元素。该方法根据操作的需要，通过将操作传递给具有定义的路由方案的操作解码器，从每个操作所需的共享资源中解码多个元素。该方法还根据操作解码器的路由信号将元素路由到消费者对共享资源执行操作和结果值。

10. 发明授权

US07979682B2 Method and system for preventing livelock due to competing updates of prediction information 有权
标题翻译：由于预测信息的竞争更新而防止活动锁定的方法和系统
公开(公告)号：US07979682B2
公开(公告)日：2011-07-12
申请号：US12051322
申请日：2008-03-19
申请人： Erik R. Altman , Vijayalakshmi Srinivasan
发明人： Erik R. Altman , Vijayalakshmi Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F9/528 , G06F9/30043 , G06F9/3842 , G06F9/3861
摘要： A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is mispredicted to form an appended instruction. A prediction override bit is set on the appended instruction. Then, the appended instruction is executed with the real event outcome.
摘要翻译：防止活动锁的系统。预测事件的结果将形成事件结果预测。将事件结果预测与要访问的基准的正确值进行比较。当事件的结果被错误预测以形成附加的指令时，指令将附加真实的事件结果。在附加的指令上设置预测覆盖位。然后，附加的指令与实际事件结果一起执行。

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