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1. 发明授权

US06829736B1 Method of testing a memory 失效
标题翻译：测试内存的方法
公开(公告)号：US06829736B1
公开(公告)日：2004-12-07
申请号：US09831657
申请日：2001-05-11
申请人： Erik Jan Marinissen , Guillaume Elisabeth Andreas Lousberg , Paul Wielage
发明人： Erik Jan Marinissen , Guillaume Elisabeth Andreas Lousberg , Paul Wielage
IPC分类号： H03M1300
CPC分类号： G11C29/44
摘要： A built-in self-diagnostic (BISD) memory device includes a two-dimension memory array provided with a redundant memory rows and columns that can be substituted for various ones in the two-dimension memory array by an external repair facility. A stimulus generator outputs multi-address test sequences to the memory array during a test mode. A response evaluator receives responses from the memory. A fault table stores evaluations of the responses, and communicates them to the external repair facility. A repair register indicates which memory columns have been intermediately scheduled for repair by the response evaluator. Column counters each accumulate the number of memory bit faults detected in a respective memory column. All are disposed in a single integrated circuit semiconductor device.
摘要翻译：内置自诊断（BISD）存储器件包括一个二维存储器阵列，其具有可由外部修复设备代替二维存储器阵列中的各种存储器行和列的冗余存储器行和列。刺激发生器在测试模式期间向存储器阵列输出多地址测试序列。响应评估器从内存接收响应。故障表存储响应的评估，并将其传达给外部维修设施。修复寄存器指示哪些内存列已被中间计划由响应评估程序进行修复。列计数器每个累加在相应存储器列中检测到的存储器位故障的数量。全部设置在单个集成电路半导体器件中。

2. 发明申请

US20140082421A1 CONTROLLED TOGGLE RATE OF NON-TEST SIGNALS DURING MODULAR SCAN TESTING OF AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路的模块化扫描测试期间的非测试信号的控制速率
公开(公告)号：US20140082421A1
公开(公告)日：2014-03-20
申请号：US13619248
申请日：2012-09-14
申请人： Erik Jan Marinissen , Sergej Deutsch
发明人： Erik Jan Marinissen , Sergej Deutsch
IPC分类号： G06F11/263
CPC分类号： G01R31/318575 , G01R31/31721 , G01R31/318552
摘要： A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module.
摘要翻译：提供了一种用于测试模块化集成电路（IC）的方法，包括：测试IC内的模块测试（MUT），同时在MUT的第一相邻模块内引起受控的切换速率; 其中，选择所述第一相邻模块内的受控切换速率，使得在所述第一相邻模块中的切换对于所述第一相邻模块的实际正常功能操作期间将具有的所述MUT的操作具有基本相同的效果。

3. 发明申请

US20100223515A1 TESTING OF AN INTEGRATED CIRCUIT THAT CONTAINS SECRET INFORMATION 有权
标题翻译：包含秘密信息的集成电路的测试
公开(公告)号：US20100223515A1
公开(公告)日：2010-09-02
申请号：US12063156
申请日：2006-08-09
申请人： Andre Krijn Nieuwland , Sandeepkumar Goel , Erik Jan Marinissen , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
发明人： Andre Krijn Nieuwland , Sandeepkumar Goel , Erik Jan Marinissen , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541 , G01R31/31719
摘要： An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.
摘要翻译：集成电路（10）包括具有耦合到功能电路（12a-c）的并行输入和输出的扫描链（14）。提供耦合到扫描链（14）的扫描链修改电路（43,47,70a-c）。当授权测试时，扫描链修改电路以通过扫描链提供正常移位路径的模式工作。当测试不被授权时，扫描链修改电路（43,47,70a-c）操作以实现移位路径中的自发动态变化，其在移位期间动态地改变集成电路的外部端子之间的移位路径的长度。在一个实施例中，通过运行的密钥比较来控制动态变化。在其他实施例中，运行密钥比较用于禁止通过扫描链的转移和/或功能电路的操作。

4. 发明授权

US07475317B2 Automatic test pattern generation 失效
标题翻译：自动测试模式生成
公开(公告)号：US07475317B2
公开(公告)日：2009-01-06
申请号：US10557965
申请日：2004-05-19
申请人： Erik Jan Marinissen , Hubertus Gerardus Hendrikus Vermeulen , Hendrik Dirk Lodewijk Hollmann
发明人： Erik Jan Marinissen , Hubertus Gerardus Hendrikus Vermeulen , Hendrik Dirk Lodewijk Hollmann
IPC分类号： G01R31/28
CPC分类号： G01R31/318371
摘要： A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From the first set of code words, a second set of code words is selected. The number of code words in the second set is equal to said number of wiring interconnects, and the selection of the second set of code words is such that the sum of the transition counts for the code words in the second set is minimized.
摘要翻译：描述了生成用于测试多个布线互连的数字测试图案的方法。生成第一组测试图案; 第一组中的测试图案的数量与所述布线互连的数量相关，并且定义第一组代码字。从第一组码字中选出第二组码字。第二组中的码字的数量等于所述布线互连的数量，并且第二组码字的选择使得第二组中的码字的转换计数的总和最小化。

5. 发明授权

US08680874B2 On-chip testing using time-to-digital conversion 有权
标题翻译：使用时间到数字转换的片上测试
公开(公告)号：US08680874B2
公开(公告)日：2014-03-25
申请号：US13194818
申请日：2011-07-29
申请人： Nikolaos Minas , Erik Jan Marinissen
发明人： Nikolaos Minas , Erik Jan Marinissen
IPC分类号： G01R27/02
CPC分类号： G01R31/2853
摘要： A method and system for testing the functionality of a through-silicon-via in an integrated circuit is disclosed. In one aspect, the functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. The comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter.
摘要翻译：公开了一种用于测试集成电路中的硅通孔的功能的方法和系统。在一个方面，通过仅从一侧测量其电容来测试功能。可以通过测量由于TSV的存在而在测量电路中引入的定时延迟来确定TSV的电容。定时延迟通过将来自测量电路的测量信号的定时与由参考电路提供的参考信号的定时进行比较来确定。使用诸如时间 - 数字转换器的数字定时测量电路进行比较。

6. 发明申请

US20100264932A1 TESTING OF AN INTEGRATED CIRCUIT THAT CONTAINS SECRET INFORMATION 有权
标题翻译：包含秘密信息的集成电路的测试
公开(公告)号：US20100264932A1
公开(公告)日：2010-10-21
申请号：US12063151
申请日：2006-08-09
申请人： Erik Jan Marinissen , Sandeepkumar Goel , Andre Krijn Nieuwland , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
发明人： Erik Jan Marinissen , Sandeepkumar Goel , Andre Krijn Nieuwland , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
IPC分类号： G01R31/02
CPC分类号： G01R31/31719 , G01R31/318533
摘要： An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown. As a result, a person that does not know which fuse elements are first fuse elements and which are second fuse elements is presented with difficulties to restore the integrated circuit to a state where test access with the danger of access to the secured information is possible.
摘要翻译：集成电路（10）包括功能电路（12a-c），其包含必须防止未授权访问的信息。集成电路包括耦合到功能电路（12a-c）的测试访问电路（14,16）和耦合到测试访问电路（14,16）的多个熔丝元件（18）。保险丝元件（18）以仅在多个第一熔丝元件（18）处于吹制状态时通过测试存取电路（14,16）可一致地访问的电路配置连接并且多个的第二熔丝元件（18）处于未吹塑状态。结果，可以在选择性地吹扫所有第一熔丝元件（18）之后测试集成电路。在测试之后，至少部分第二熔丝元件（18）被吹塑。结果，不知道哪些熔丝元件是第一熔丝元件并且是第二熔丝元件的人被呈现难以将集成电路恢复到具有访问安全信息的危险的测试访问是可能的状态。

7. 发明授权

US08914689B2 Controlled toggle rate of non-test signals during modular scan testing of an integrated circuit 有权
标题翻译：在集成电路的模块化扫描测试期间，非测试信号的控制切换速率
公开(公告)号：US08914689B2
公开(公告)日：2014-12-16
申请号：US13619248
申请日：2012-09-14
申请人： Erik Jan Marinissen , Sergej Deutsch
发明人： Erik Jan Marinissen , Sergej Deutsch
IPC分类号： G01R31/28
CPC分类号： G01R31/318575 , G01R31/31721 , G01R31/318552
摘要： A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module.
摘要翻译：提供了一种用于测试模块化集成电路（IC）的方法，包括：测试IC内的模块测试（MUT），同时在MUT的第一相邻模块内引起受控的切换速率; 其中，选择所述第一相邻模块内的受控切换速率，使得在所述第一相邻模块中的切换对于所述第一相邻模块的实际正常功能操作期间将具有的所述MUT的操作具有基本相同的效果。

8. 发明授权

US08773157B2 Test circuit for testing through-silicon-vias in 3D integrated circuits 有权
标题翻译：用于在3D集成电路中测试硅通孔的测试电路
公开(公告)号：US08773157B2
公开(公告)日：2014-07-08
申请号：US13174617
申请日：2011-06-30
申请人： Mustafa Badaroglu , Erik Jan Marinissen , Paul Marchal
发明人： Mustafa Badaroglu , Erik Jan Marinissen , Paul Marchal
IPC分类号： G01R31/26 , G01R31/00
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31717 , H01L22/34
摘要： A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.
摘要翻译：公开了在每个制造阶段在三维集成电路（IC）中测试穿硅通孔（TSV）的测试电路和方法。在一个方面，该方法包括测试每个单独的TSV，TSV未测试中的TSV测试之间的短路，以及紧邻的TSV之间的短路以及TSV未测试之间的连接以及 ICs。测试电路具有通过上拉电阻连接到电源的三个可切换电流路径，并且切换：校准路径，短路径和电流测量路径。电源连接到测量路径，校准路径和短路通过相应的下拉电阻连接到地。对于每个TSV低于测试，通过关闭开关的不同组合来选择所需的操作模式。在每种运行模式下流过上拉电阻的电流表示TSV未测试是否已通过或失败。

9. 发明申请

US20130002272A1 FAULT MODE CIRCUITS 有权
标题翻译：故障电路
公开(公告)号：US20130002272A1
公开(公告)日：2013-01-03
申请号：US13174617
申请日：2011-06-30
申请人： Mustafa Badaroglu , Erik Jan Marinissen , Paul Marchal
发明人： Mustafa Badaroglu , Erik Jan Marinissen , Paul Marchal
IPC分类号： G01R31/02
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31717 , H01L22/34
摘要： A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.
摘要翻译：公开了在每个制造阶段在三维集成电路（IC）中测试穿硅通孔（TSV）的测试电路和方法。在一个方面，该方法包括测试每个单独的TSV，TSV未测试中的TSV测试之间的短路，以及紧邻的TSV之间的短路以及TSV未测试之间的连接以及 ICs。测试电路具有通过上拉电阻连接到电源的三个可切换电流路径，并且切换：校准路径，短路径和电流测量路径。电源连接到测量路径，校准路径和短路通过相应的下拉电阻连接到地。对于每个TSV低于测试，通过关闭开关的不同组合来选择所需的操作模式。在每种运行模式下流过上拉电阻的电流表示TSV未测试是否已通过或失败。

10. 发明申请

US20120025846A1 ON-CHIP TESTING USING TIME-TO-DIGITAL CONVERSION 有权
标题翻译：使用时间到数字转换的片上测试
公开(公告)号：US20120025846A1
公开(公告)日：2012-02-02
申请号：US13194818
申请日：2011-07-29
申请人： Nikolaos Minas , Erik Jan Marinissen
发明人： Nikolaos Minas , Erik Jan Marinissen
IPC分类号： G01R27/02
CPC分类号： G01R31/2853
摘要： A method and system for testing the functionality of a through-silicon-via in an integrated circuit is disclosed. In one aspect, the functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. The comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter.
摘要翻译：公开了一种用于测试集成电路中的硅通孔的功能的方法和系统。在一个方面，通过仅从一侧测量其电容来测试功能。可以通过测量由于TSV的存在而在测量电路中引入的定时延迟来确定TSV的电容。定时延迟通过将来自测量电路的测量信号的定时与由参考电路提供的参考信号的定时进行比较来确定。使用诸如时间 - 数字转换器的数字定时测量电路进行比较。

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