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1. 发明授权

US08680874B2 On-chip testing using time-to-digital conversion 有权
标题翻译：使用时间到数字转换的片上测试
公开(公告)号：US08680874B2
公开(公告)日：2014-03-25
申请号：US13194818
申请日：2011-07-29
申请人： Nikolaos Minas , Erik Jan Marinissen
发明人： Nikolaos Minas , Erik Jan Marinissen
IPC分类号： G01R27/02
CPC分类号： G01R31/2853
摘要： A method and system for testing the functionality of a through-silicon-via in an integrated circuit is disclosed. In one aspect, the functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. The comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter.
摘要翻译：公开了一种用于测试集成电路中的硅通孔的功能的方法和系统。在一个方面，通过仅从一侧测量其电容来测试功能。可以通过测量由于TSV的存在而在测量电路中引入的定时延迟来确定TSV的电容。定时延迟通过将来自测量电路的测量信号的定时与由参考电路提供的参考信号的定时进行比较来确定。使用诸如时间 - 数字转换器的数字定时测量电路进行比较。

2. 发明申请

US20110102011A1 METHOD AND DEVICE FOR TESTING TSVS IN A 3D CHIP STACK 有权
标题翻译：用于在3D芯片堆栈中测试TSVS的方法和装置
公开(公告)号：US20110102011A1
公开(公告)日：2011-05-05
申请号：US12891658
申请日：2010-09-27
申请人： Geert Van der Plas , Erik-Jan Marinissen , Nikolaos Minas , Paul Marchal
发明人： Geert Van der Plas , Erik-Jan Marinissen , Nikolaos Minas , Paul Marchal
IPC分类号： G01R31/26 , H01L23/528
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31855 , H01L22/34 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06596
摘要： A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.
摘要翻译：公开了一种用于在3D芯片堆栈中测试贯穿衬底通孔（TSV）的方法和装置。一方面，3D芯片堆栈至少包括具有第一电路的第一管芯和具有第二电路的第二管芯。第一模具还包括用于在第一电路和第二电路之间提供电连接的至少一个第一TSV。第一裸片还包括测试电路和电连接在第一TSV和测试电路之间的至少一个第二TSV。第一TSV和第二TSV之间的电连接在第二管芯的外部。在一个方面，这允许测试第一裸片中的第一TSV，即使第二裸片没有设置专用测试电路。

3. 发明申请

US20120025846A1 ON-CHIP TESTING USING TIME-TO-DIGITAL CONVERSION 有权
标题翻译：使用时间到数字转换的片上测试
公开(公告)号：US20120025846A1
公开(公告)日：2012-02-02
申请号：US13194818
申请日：2011-07-29
申请人： Nikolaos Minas , Erik Jan Marinissen
发明人： Nikolaos Minas , Erik Jan Marinissen
IPC分类号： G01R27/02
CPC分类号： G01R31/2853
摘要： A method and system for testing the functionality of a through-silicon-via in an integrated circuit is disclosed. In one aspect, the functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. The comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter.
摘要翻译：公开了一种用于测试集成电路中的硅通孔的功能的方法和系统。在一个方面，通过仅从一侧测量其电容来测试功能。可以通过测量由于TSV的存在而在测量电路中引入的定时延迟来确定TSV的电容。定时延迟通过将来自测量电路的测量信号的定时与由参考电路提供的参考信号的定时进行比较来确定。使用诸如时间 - 数字转换器的数字定时测量电路进行比较。

4. 发明授权

US08593170B2 Method and device for testing TSVS in a 3D chip stack 有权
标题翻译：用于在3D芯片堆栈中测试TSVS的方法和设备
公开(公告)号：US08593170B2
公开(公告)日：2013-11-26
申请号：US12891658
申请日：2010-09-27
申请人： Geert Van der Plas , Erik-Jan Marinissen , Nikolaos Minas , Paul Marchal
发明人： Geert Van der Plas , Erik-Jan Marinissen , Nikolaos Minas , Paul Marchal
IPC分类号： G01R31/02 , G01R31/26 , G01R27/28 , H03K19/003 , H03K19/00
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31855 , H01L22/34 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06596
摘要： A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.
摘要翻译：公开了一种用于在3D芯片堆栈中测试贯穿衬底通孔（TSV）的方法和装置。一方面，3D芯片堆栈至少包括具有第一电路的第一管芯和具有第二电路的第二管芯。第一模具还包括用于在第一电路和第二电路之间提供电连接的至少一个第一TSV。第一裸片还包括测试电路和电连接在第一TSV和测试电路之间的至少一个第二TSV。第一TSV和第二TSV之间的电连接在第二管芯的外部。在一个方面，这允许测试第一裸片中的第一TSV，即使第二裸片没有设置专用测试电路。

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