专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06879276B2 Split cell bowtie digital to analog converter and method 失效
标题翻译：分离电池bowtie数字到模拟转换器和方法
公开(公告)号：US06879276B2
公开(公告)日：2005-04-12
申请号：US10739860
申请日：2003-12-18
申请人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder , Christopher B. Langit , Roger N. Kosaka
发明人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder , Christopher B. Langit , Roger N. Kosaka
IPC分类号： H03M1/06 , H03M1/74 , H03M1/66
CPC分类号： H03M1/0643 , H03M1/745
摘要： A DAC (10) including an operational amplifier (12) having an input terminal; a plurality of current paths coupled to the input terminal; a plurality of current sources (I1/2 -I4/2); and an arrangement (11) for switchably coupling current from at least two of the cells to a respective one of the paths in response to an input signal. In a specific embodiment, the inventive DAC (10) further includes a first resistive element (2R1-2R4) disposed in each of the current paths, a second resistive element (R1-R4) disposed between the current paths, and a feedback resistor (RF) disposed between an output terminal of the amplifier and the input terminal thereof. In the illustrative embodiment, the coupling arrangement includes a plurality of switches (SW1-SW4); each of the switches is adapted to switch half of the current from a first source and half of the current from a second source into a respective one of the paths. The invention is adapted to lower the distortion of digital to analog converters by improving differential nonlinearities and integral nonlinearities, caused primarily by current source gradient errors, without the need for trimming.
摘要翻译：包括具有输入端的运算放大器（12）的DAC（10）耦合到所述输入端的多个电流通路; 多个电流源（I1 / 2 -I4 / 2）; 以及用于响应于输入信号将来自至少两个单元的电流可切换地耦合到相应的一个路径的装置（11）。在具体实施例中，本发明的DAC（10）还包括设置在每个电流路径中的第一电阻元件（2R1-2R4），设置在电流路径之间的第二电阻元件（R1-R4）和反馈电阻器 RF）设置在放大器的输出端和其输入端之间。在说明性实施例中，耦合装置包括多个开关（SW1-SW4）; 每个开关适于将来自第一源的电流的一半和来自第二源的电流的一半切换到相应的一个路径。本发明适用于通过改善主要由电流源梯度误差引起的差分非线性和积分非线性来降低数模转换器的失真，而不需要修整。

2. 发明授权

US07098700B2 Low power output driver 有权
标题翻译：低功率输出驱动器
公开(公告)号：US07098700B2
公开(公告)日：2006-08-29
申请号：US10886850
申请日：2004-07-08
申请人： Nanci Martinez , Seth L. Everton , Erick M. Hirata , Lloyd F. Linder
发明人： Nanci Martinez , Seth L. Everton , Erick M. Hirata , Lloyd F. Linder
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/01812 , H03K17/662
摘要： An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.
摘要翻译：输出驱动程序新颖的输出驱动器包括用于接收输入信号并根据其在输出节点处产生输出信号的第一电路，用于向输出节点施加可变电流的第二电路和用于控制变量的幅度的第三电路电流根据输入信号。在说明性实施例中，第三电路适于根据输入信号产生控制电流，并且第二电路包括适于接收控制电流的电流镜，并将控制电流的缩放版本输出到输出节点。

3. 发明授权

US06404228B1 Apparatus for translating digital signals 失效
标题翻译：用于转换数字信号的装置
公开(公告)号：US06404228B1
公开(公告)日：2002-06-11
申请号：US09005411
申请日：1998-01-09
申请人： Ralph T. Luna , Lloyd F. Linder , Erick M. Hirata
发明人： Ralph T. Luna , Lloyd F. Linder , Erick M. Hirata
IPC分类号： H03K190175
CPC分类号： H03K19/01806 , H03K19/01837 , H03K19/0826
摘要： An apparatus for selectably converting emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL) signals to negative complimentary metal oxide semiconductor (NCMOS) signals is disclosed. The apparatus uses an input level shifter, a secondary level shifter, and an output buffer to convert the ECL and PECL differential signals to single-ended signals. The apparatus also includes a disable output function for disabling the output of the output buffer. The apparatus may be integrated multiple times on a substrate containing NCMOS circuitry, thereby allowing the NCMOS circuitry to be driven by differential signals. Alternatively, the present invention may be integrated multiple times onto a single substrate to create a dedicated universal translator.
摘要翻译：公开了一种用于将发射极耦合逻辑（ECL）和正发射极耦合逻辑（PECL）信号可选择地转换为负互补金属氧化物半导体（NCMOS）信号的装置。该装置使用输入电平移位器，次级电平移位器和输出缓冲器来将ECL和PECL差分信号转换为单端信号。该装置还包括用于禁止输出缓冲器的输出的禁用输出功能。该装置可以在包含NCMOS电路的基板上多次集成，从而允许NCMOS电路由差分信号驱动。或者，本发明可以多次集成到单个基板上以创建专用通用转换器。

4. 发明授权

US5859569A Current feedback differential amplifier clamp 失效
标题翻译：电流反馈差分放大器钳位
公开(公告)号：US5859569A
公开(公告)日：1999-01-12
申请号：US843200
申请日：1997-04-14
申请人： Hieu M. Le , Lloyd F. Linder , Erick M. Hirata , Benjamin Felder , Roger N. Kosaka , Donald G. McMullin , Kelvin T. Tran
发明人： Hieu M. Le , Lloyd F. Linder , Erick M. Hirata , Benjamin Felder , Roger N. Kosaka , Donald G. McMullin , Kelvin T. Tran
IPC分类号： H03F1/52 , H03F3/30 , H02H7/20 , H03M1/12
CPC分类号： H03F3/3076 , H03F1/52
摘要： A current steering circuit diverts bias current from a differential current summing amplifier's front end when the differential input exceeds a safe threshold level, thus preventing the amplifier's output stage from being overdriven. Diverting the front end's bias currents also turns off transistors within the amplifier's front end and thus protects the front end from damage which may otherwise result from excessive input signals.
摘要翻译：当差分输入超过安全阈值电平时，电流转向电路将偏置电流从差分电流求和放大器的前端转移，从而防止放大器的输出级过载。转向前端的偏置电流也会关闭放大器前端的晶体管，从而保护前端免受过大输入信号造成的损坏。

5. 发明申请

US20110221486A1 DIGITALLY CALIBRATED HIGH SPEED CLOCK DISTRIBUTION 有权
标题翻译：数字校准高速时钟分配
公开(公告)号：US20110221486A1
公开(公告)日：2011-09-15
申请号：US12723285
申请日：2010-03-12
申请人： Erick M. Hirata , Lloyd F. Linder
发明人： Erick M. Hirata , Lloyd F. Linder
IPC分类号： H03L7/06
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/087
摘要： An electronic circuit for distributing a clock signal to a plurality of clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; and loop filters for generating and transmitting respective DC voltage feedback signals.The circuit further includes current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.
摘要翻译：用于将时钟信号分配到多个时钟目的地的电子电路包括相位调整电路，用于响应于从相应的一个时钟目的地的相应DC电压反馈信号接收来调整时钟目标的相应一个时钟的时钟的相移 ; 相位检测器，用于根据最近的相邻时钟目的地检测相应的一个时钟目的地的时钟信号的相移; 以及用于产生和发送各个DC电压反馈信号的环路滤波器。该电路还包括电流源，每个电流源被配置为接收相应的直流电压反馈信号，并根据所述相应的直流电压反馈信号将相应的电流输出到相应的一个相位调整电路，以调整时钟信号的相位偏移相应的时钟目的地之一。

6. 发明授权

US5990815A Monolithic circuit and method for adding a randomized dither signal to the fine quantizer element of a subranging analog-to digital converter (ADC) 失效
标题翻译：用于将随机抖动信号添加到子矩阵模数转换器（ADC）的精细量化器元件的单片电路和方法，
公开(公告)号：US5990815A
公开(公告)日：1999-11-23
申请号：US941457
申请日：1997-09-30
申请人： Lloyd F. Linder , Erick M. Hirata , Benjamin Felder , William W. Cheng , Robert Tso
发明人： Lloyd F. Linder , Erick M. Hirata , Benjamin Felder , William W. Cheng , Robert Tso
IPC分类号： H03M1/06 , H03M1/20
CPC分类号： H03M1/0641
摘要： A dither circuit is monolitically integrated with a subranging ADC to add a dither signal at the input of the ADC's fine quantizer element to randomize its nonlinear quantization level errors. Because the subranging ADC has at least one overlap bit, the amplitude of the dither signal can range up to at least 2.sup.M-1 LSBs of the fine quantizer without saturating it. The digital equivalent of the dither signal is subtracted at the output of the fine quantizer to maintain the ADC's overall SNR. The randomization of only the fine quantizer element avoids gaining up the nonlinear errors associated with the dither signal itself thereby improving the overall SNR. This approach optimizes performance for small input signals while sacrificing flexibility to correct other sources of error.
摘要翻译：抖动电路与subranging ADC单独集成，以在ADC的精细量化器元件的输入端添加抖动信号，以随机化其非线性量化级误差。由于Subranging ADC具有至少一个重叠位，所以抖动信号的幅度可以至少达到精细量化器的2M-1 LSB，而不使其饱和。在精细量化器的输出处减去抖动信号的数字等效值，以保持ADC的整体SNR。只有精细量化器元件的随机化避免增加与抖动信号本身相关联的非线性误差，从而提高整体SNR。这种方法优化了小输入信号的性能，同时牺牲了纠正其他错误源的灵活性。

7. 发明授权

US5973631A Test circuit and method of trimming a unary digital-to-analog converter (DAC) in a subranging analog-to-digital converter (ADC) 失效
标题翻译：在子模式数模转换器（ADC）中调整一元数模转换器（DAC）的测试电路和方法
公开(公告)号：US5973631A
公开(公告)日：1999-10-26
申请号：US9612
申请日：1998-01-20
申请人： Donald G. McMullen , Erick M. Hirata , Lloyd F. Linder , Adam Wu
发明人： Donald G. McMullen , Erick M. Hirata , Lloyd F. Linder , Adam Wu
IPC分类号： H03M1/10 , H03M1/74 , H03M1/06
CPC分类号： H03M1/1057 , H03M1/747
摘要： In a subranging ADC, the unary DAC is trimmed by walking through its transfer function while toggling an offset cell at the input to the coarse quantizer and a reference cell in the DAC such that the reference cell is substituted for the cell under test on alternating cycles to provide the last lsb of the reconstructed signal. A test circuit measures the voltage at the output of the summing amplifier for both conditions and generates an error voltage in which the common mode terms have been rejected. The cell under test is then laser trimmed to reduce the error voltage until the cell's DNL error is within an error bound of a tolerance. In one embodiment, the tolerance is dithered to improve spur free dynamic range.
摘要翻译：在子矩阵ADC中，一元DAC通过走过其传递函数来修剪，同时在粗略量化器的输入处切换偏移单元，并且DAC中的参考单元，使得参考单元以交替周期代替被测单元以提供重建信号的最后lsb。一个测试电路测量两个条件下求和放大器输出端的电压，并产生一个错误电压，其中共模式项已被拒绝。然后对被测电池进行激光修整以减小误差电压，直到电池的DNL误差在公差的误差范围内。在一个实施例中，该公差被抖动以改善无杂散动态范围。

8. 发明授权

US08179173B2 Digitally calibrated high speed clock distribution 有权
标题翻译：数字校准的高速时钟分配
公开(公告)号：US08179173B2
公开(公告)日：2012-05-15
申请号：US12723285
申请日：2010-03-12
申请人： Erick M. Hirata , Lloyd F. Linder
发明人： Erick M. Hirata , Lloyd F. Linder
IPC分类号： H03L7/00 , H03H11/16
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/087
摘要： An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.
摘要翻译：用于将时钟信号分配到多个时钟目的地的电子电路包括相位调整电路，用于响应于从相应的一个时钟目的地的相应DC电压反馈信号接收来调整在相应的一个时钟目的地的时钟的相移; 相位检测器，用于根据最近的相邻时钟目的地检测相应的一个时钟目的地的时钟信号的相移; 环路滤波器，用于产生和发送相应的直流电压反馈信号; 电流源，每个被配置为接收相应的DC电压反馈信号，并且根据所述各个DC电压反馈信号将相应的电流输出到相应的一个相位调整电路，以调整相应的一个电压反馈信号的时钟信号的相移时钟目的地。

9. 发明授权

US07154421B2 DNL/INL trim techniques for comparator based analog to digital converters 有权
标题翻译：用于基于比较器的模数转换器的DNL / INL微调技术
公开(公告)号：US07154421B2
公开(公告)日：2006-12-26
申请号：US10890443
申请日：2004-07-12
申请人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder
发明人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder
IPC分类号： H03M1/06
CPC分类号： H03K5/2418 , H03M1/1057 , H03M1/1061 , H03M1/363
摘要： A trimmable comparator. The novel comparator includes a first circuit for comparing first and second input signals and in accordance therewith generating first and second output signals, and a second circuit for adding an adjustable current to the first output signal such that the comparator is in a transition state when the first and/or second input signals are at desired levels. The comparator may also include a third circuit for adding an adjustable current to the second output signal. In the illustrative embodiments, the second and third circuits are implemented using adjustable current sources with trimmable resistors, or using digital to analog converters. The novel comparators may be used in an analog to digital converter to allow the converter thresholds to be adjusted to desired levels.
摘要翻译：可调整比较器。新颖的比较器包括用于比较第一和第二输入信号并根据其产生第一和第二输出信号的第一电路和用于将可调电流加到第一输出信号的第二电路，使得当比较器处于转换状态时第一和/或第二输入信号处于期望的电平。比较器还可以包括用于将可调电流加到第二输出信号的第三电路。在说明性实施例中，第二和第三电路使用具有可调节电阻器的可调电流源或使用数模转换器来实现。新颖的比较器可以用在模数转换器中以允许将转换器阈值调整到期望的水平。

10. 发明授权

US07095347B2 Digitally trimmed DAC cell 有权
标题翻译：数字修整DAC电池
公开(公告)号：US07095347B2
公开(公告)日：2006-08-22
申请号：US10715262
申请日：2003-11-17
申请人： Erick M. Hirata , Roger N. Kosaka , Christopher B. Langit , Lloyd F. Linder
发明人： Erick M. Hirata , Roger N. Kosaka , Christopher B. Langit , Lloyd F. Linder
IPC分类号： H03M1/66
CPC分类号： G05F3/22
摘要： A digitally trimmed current source. The novel current source includes a first circuit for generating a current in response to an applied voltage and a resistance variable in response to a control signal, and a second circuit for supplying the control signal. The first circuit includes a resistive network comprised of a plurality of resistors; a plurality of switches, each switch coupled to one of the resistors and adapted to selectively switch the resistor in and out of the resistive network in response to the control signal; and a transistor adapted to apply a voltage across the resistive network to generate a current.
摘要翻译：数字修剪电流源。新颖的电流源包括响应于施加的电压产生电流的第一电路和响应于控制信号的电阻变量，以及用于提供控制信号的第二电路。第一电路包括由多个电阻组成的电阻网络; 多个开关，每个开关耦合到所述电阻器之一并且适于响应于所述控制信号选择性地将所述电阻器进入和流出所述电阻网络; 以及适于在电阻网络上施加电压以产生电流的晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式