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1. 发明授权

US06894726B2 High-definition de-interlacing and frame doubling circuit and method 有权
标题翻译：高分辨率去隔行和帧倍增电路及方法
公开(公告)号：US06894726B2
公开(公告)日：2005-05-17
申请号：US10190282
申请日：2002-07-05
申请人： Eric Stephen Carlsgaard , David Leon Simpson , Michael Evan Crabb
发明人： Eric Stephen Carlsgaard , David Leon Simpson , Michael Evan Crabb
IPC分类号： H04N7/01 , H04N5/44 , H04N11/20
CPC分类号： H04N7/0132 , H04N7/012 , Y10S348/911
摘要： A combined de-interlacing and frame doubling system (114, 114′ and 114″) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism (116, 116′ and 116″) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit (11401, 1140′1, 1140″) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.
摘要翻译：组合的去隔行和帧倍增系统（114,114'和114“）有利地用于以现场速率的两倍将当前视频数据的连续行去隔行，以产生适于在显示设备上显示的输出比特流，利用逐行扫描。根据本原理的去隔行和帧倍增系统包括用于存储具有规定场速的隔行扫描视频的至少一帧的帧存储机构（116,116'和116“）。至少一个去隔行电路（1140,1401,1140“，1140”）以至少两个视场数据从存储器机构以至少两次用于在场周期的一半中执行完全去隔行扫描功能的场速率，以产生用于在显示装置处接收的渐进的帧双倍信号。

2. 发明授权

US07468754B2 High-definition de-interlacing and frame doubling circuit and method 有权
标题翻译：高分辨率去隔行和帧倍增电路及方法
公开(公告)号：US07468754B2
公开(公告)日：2008-12-23
申请号：US11036920
申请日：2005-01-14
申请人： Eric Stephen Carlsgaard , David Leon Simpson , Michael Evan Crabb
发明人： Eric Stephen Carlsgaard , David Leon Simpson , Michael Evan Crabb
IPC分类号： H04N7/01 , H04N11/20
CPC分类号： H04N7/0132 , H04N7/012 , Y10S348/911
摘要： A combined de-interlacing and frame doubling system (114, 114′ and 114″) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism (116, 116′ and 116″) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit (11401, 1140′1, 1140″) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.
摘要翻译：组合的去隔行和帧倍增系统（114,114'和114“）有利地用于以现场速率的两倍将当前视频数据的连续行去隔行，以产生适于在显示设备上显示的输出比特流，利用逐行扫描。根据本原理的去隔行和帧倍增系统包括用于存储具有规定场速的隔行扫描视频的至少一帧的帧存储机构（116,116'和116“）。至少一个去隔行电路（11401,1140'1,1140“）以至少两倍于场速率的速率从存储器机构拉出至少两个视频数据场，用于执行一半的完全去隔行功能以产生用于在显示设备处接收的渐进的帧双倍信号。

3. 发明授权

US06839779B2 Counting a number of occurrences of a first RTS (ready to send) and a first RTR (ready to receive) signals for limiting a data transfer bandwidth through handshake suppression 有权
标题翻译：计数第一个RTS（准备发送）和第一个RTR（准备接收）信号的数量，以便通过握手抑制限制数据传输带宽
公开(公告)号：US06839779B2
公开(公告)日：2005-01-04
申请号：US10490009
申请日：2002-09-19
申请人： David Leon Simpson , Didier Joseph Marie Velez
发明人： David Leon Simpson , Didier Joseph Marie Velez
IPC分类号： H04L29/08 , G06F3/00 , G06F13/10 , G06F13/38 , G06F13/40 , G06F13/42 , H04L12/413 , H04L12/56
CPC分类号： H04L47/10 , G06F13/4054 , G06F13/4286 , H04L12/40032 , H04L12/4013 , H04L41/00
摘要： An apparatus for limiting a data transfer bandwidth through handshake suppression is configured to generate a first reset signal, generate a second reset signal a predetermined number of clock cycles after generating the first reset signal, generate a handshake count representing a number of receptions, between the first reset signal and the second reset signal, of a first Ready to Send (“RTS”) handshake signal and a first Ready to Receive (“RTR”) handshake signal, and disable a second RTR handshake signal and the first RTS handshake signal based on a comparison of the handshake count and a maximum value.

4. 发明授权

US07031206B2 Digital line delay using a single port memory 有权
标题翻译：使用单端口内存的数字线路延迟
公开(公告)号：US07031206B2
公开(公告)日：2006-04-18
申请号：US10490015
申请日：2002-09-19
申请人： Paul Dean Filliman , Michael Dwayne Knox , David Leon Simpson
发明人： Paul Dean Filliman , Michael Dwayne Knox , David Leon Simpson
IPC分类号： G11C7/00 , G06F13/00
CPC分类号： H04N9/8042 , H04N5/04 , H04N5/14 , H04N5/772 , H04N5/775 , H04N5/781 , H04N5/85 , H04N5/907 , H04N7/01
摘要： An apparatus for delaying video line data between a sending device and a receiving device is provided. The apparatus includes a single port random access memory (“RAM”) and a processing arrangement including a first storage device coupled to the RAM and a second storage device coupled to the RAM.
摘要翻译：提供一种用于在发送设备和接收设备之间延迟视频行数据的设备。该装置包括单端口随机存取存储器（“RAM”）和包括耦合到RAM的第一存储装置和耦合到RAM的第二存储装置的处理装置。

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