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1. 发明授权

US07143267B2 Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor 失效
标题翻译：分区预取寄存器以防止至少部分不一致的预取信息存储在多线程处理器的预取寄存器中
公开(公告)号：US07143267B2
公开(公告)日：2006-11-28
申请号：US10425424
申请日：2003-04-28
申请人： Eric J. Fluhr , Cathy May , Balaram Sinharoy
发明人： Eric J. Fluhr , Cathy May , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/383 , G06F9/30101 , G06F9/3851 , G06F12/0862
摘要： A method and multithreaded processor for dynamically reallocating prefetch registers upon the processor switching modes of operation. An execution unit may be coupled to a prefetch engine where the execution unit may be configured to receive prefetch instructions regarding prefetching data. The prefetch engine may comprise a plurality of prefetch registers. The execution unit may further be configured to load the plurality of prefetch registers with information regarding prefetching data obtained from the prefetch instructions. In a single thread mode of operation, the plurality of prefetch registers are allocated to be accessed by either a first or a second thread. In a multithread mode of operation, the plurality of prefetch registers are allocated to be accessed among the first and second threads.
摘要翻译：一种用于在处理器切换操作模式上动态地重新分配预取寄存器的方法和多线程处理器。执行单元可以耦合到预取引擎，其中执行单元可以被配置为接收关于预取数据的预取指令。预取引擎可以包括多个预取寄存器。执行单元还可以被配置为使用关于从预取指令获得的预取数据的信息来加载多个预取寄存器。在单线程操作模式中，多个预取寄存器被分配以由第一或第二线程访问。在多线程操作模式中，分配多个预取寄存器以在第一和第二线程之间被访问。

2. 发明申请

US20100268885A1 SPECIFYING AN ACCESS HINT FOR PREFETCHING LIMITED USE DATA IN A CACHE HIERARCHY 失效
标题翻译：指定访问提示用于缓存缓存中的有限使用数据
公开(公告)号：US20100268885A1
公开(公告)日：2010-10-21
申请号：US12424681
申请日：2009-04-16
申请人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
发明人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache.
摘要翻译：一种用于指定预取有限使用数据的访问提示的系统和方法。处理单元接收具有指示给处理单元的访问提示的数据高速缓存块触摸（DCBT）指令，即在数据处理系统上执行的程序可以很快访问在DCBT指令内寻址的高速缓存块。访问提示包含在存储在DCBT指令的子字段中的代码点中。响应于检测到代码点被设置为特定值，DCBT指令中寻址的数据被预取到低级缓存中的条目中。然后可以将条目作为较低级别高速缓存中的多个条目的最近最少使用的条目来更新。响应于将新的高速缓存块提取到高速缓存，预取的高速缓存块被抛出高速缓存。

3. 发明授权

US08140759B2 Specifying an access hint for prefetching partial cache block data in a cache hierarchy 失效
标题翻译：指定用于在缓存层次结构中预取部分高速缓存块数据的访问提示
公开(公告)号：US08140759B2
公开(公告)日：2012-03-20
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

4. 发明申请

US20100268886A1 SPECIFYING AN ACCESS HINT FOR PREFETCHING PARTIAL CACHE BLOCK DATA IN A CACHE HIERARCHY 失效
标题翻译：指定访问提示用于缓存高速缓存中的部分缓存块数据
公开(公告)号：US20100268886A1
公开(公告)日：2010-10-21
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

5. 发明申请

US20090193233A1 Mechanism for Avoiding Check Stops in Speculative Accesses While Operating in Real Mode 失效
标题翻译：在实模式下操作时避免检测停止的机制
公开(公告)号：US20090193233A1
公开(公告)日：2009-07-30
申请号：US12043747
申请日：2008-03-06
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/318
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

6. 发明授权

US07370177B2 Mechanism for avoiding check stops in speculative accesses while operating in real mode 失效
标题翻译：在实模式下运行时避免检测停止的机制
公开(公告)号：US07370177B2
公开(公告)日：2008-05-06
申请号：US10424527
申请日：2003-04-25
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

7. 发明授权

US08176254B2 Specifying an access hint for prefetching limited use data in a cache hierarchy 失效
标题翻译：指定在缓存层次结构中预取有限使用数据的访问提示
公开(公告)号：US08176254B2
公开(公告)日：2012-05-08
申请号：US12424681
申请日：2009-04-16
申请人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
发明人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache.
摘要翻译：一种用于指定预取有限使用数据的访问提示的系统和方法。处理单元接收具有指示给处理单元的访问提示的数据高速缓存块触摸（DCBT）指令，即在数据处理系统上执行的程序可以很快访问在DCBT指令内寻址的高速缓存块。访问提示包含在存储在DCBT指令的子字段中的代码点中。响应于检测到代码点被设置为特定值，DCBT指令中寻址的数据被预取到低级缓存中的条目中。然后可以将条目作为较低级别高速缓存中的多个条目的最近最少使用的条目来更新。响应于将新的高速缓存块提取到高速缓存，预取的高速缓存块被抛出高速缓存。

8. 发明授权

US07949859B2 Mechanism for avoiding check stops in speculative accesses while operating in real mode 失效
标题翻译：在实模式下运行时避免检测停止的机制
公开(公告)号：US07949859B2
公开(公告)日：2011-05-24
申请号：US12043747
申请日：2008-03-06
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

9. 发明授权

US09244846B2 Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses 有权
标题翻译：确保交易存储访问的因果关系与非事务性存储访问进行交互
公开(公告)号：US09244846B2
公开(公告)日：2016-01-26
申请号：US13543325
申请日：2012-07-06
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08 , G06F9/46
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
摘要翻译：数据处理系统为分布式共享存储器系统实现弱一致性存储器模型。数据处理系统在多个处理器核心上同时执行存储器事务内的一个或多个事务存储器指令和一个或多个非事务存储器指令。一个或多个非事务存储器指令包括非事务存储指令。数据处理系统只是为了响应于关于存储器事务的非事务性存储指令的因果关系的强制而将存储器事务提交给分布式共享存储器系统。

10. 发明申请

US20140013055A1 ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES 审中-公开
标题翻译：确保与非交易存储访问交互的交易存储访问的原理
公开(公告)号：US20140013055A1
公开(公告)日：2014-01-09
申请号：US13777161
申请日：2013-02-26
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
摘要翻译：数据处理系统为分布式共享存储器系统实现弱一致性存储器模型。数据处理系统在多个处理器核心上同时执行存储器事务内的一个或多个事务存储器指令和一个或多个非事务存储器指令。一个或多个非事务存储器指令包括非事务存储指令。数据处理系统只是为了响应于关于存储器事务的非事务性存储指令的因果关系的强制而将存储器事务提交给分布式共享存储器系统。

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