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1. 发明申请

US20050058222A1 Analog front-end having built-in equalization and applications thereof 有权
标题翻译：模拟前端内置均衡及其应用
公开(公告)号：US20050058222A1
公开(公告)日：2005-03-17
申请号：US10659803
申请日：2003-09-11
申请人： William Black , Charles Boecker , Eric Groen
发明人： William Black , Charles Boecker , Eric Groen
IPC分类号： H04L25/02 , H04L27/06
CPC分类号： H04L25/03885
摘要： An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.
摘要翻译：具有内置均衡的模拟前端包括控制模块和可调增益级。控制模块可操作地耦合以基于向模拟前端提供高速串行数据的信道的信道响应提供频率响应设置。可调增益级包括频率相关负载和放大器输入部分。频率相关负载根据频率响应设置进行调整。放大器输入部分可操作地耦合到与频率相关的负载并接收高速串行数据。结合频率依赖负载，放大器输入部分放大并均衡高速串行数据，以产生放大和均衡的串行数据。

2. 发明申请

US20050058187A1 Programmable logic device including programmable multi-gigabit transceivers 有权
标题翻译：可编程逻辑器件包括可编程的多吉比特收发器
公开(公告)号：US20050058187A1
公开(公告)日：2005-03-17
申请号：US10661016
申请日：2003-09-11
申请人： Eric Groen , Charles Boecker , William Black , Scott Irwin , Joseph Kryzak , Yiqin Chen , Andrew Jenkins , Aaron Hoelscher
发明人： Eric Groen , Charles Boecker , William Black , Scott Irwin , Joseph Kryzak , Yiqin Chen , Andrew Jenkins , Aaron Hoelscher
IPC分类号： G06F15/78 , H04L25/14 , H04B1/38
CPC分类号： H04L25/14
摘要： A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.
摘要翻译：可编程逻辑器件包括多个可编程的多吉比特收发器，可编程逻辑结构和控制模块。根据多个收发器设置，多个可编程的多吉比特收发器中的每一个被单独编程为期望的收发操作模式。可编程逻辑结构可操作地耦合到多个可编程的多吉比特收发器，并且被配置为处理经由多吉比特收发器收发的数据的至少一部分。控制模块可操作地耦合以基于可编程逻辑器件的期望操作模式产生多个收发器设置。

3. 发明申请

US20050057315A1 Ring oscillator with peaking stages 有权
公开(公告)号：US20050057315A1
公开(公告)日：2005-03-17
申请号：US10659978
申请日：2003-09-11
申请人： Eric Groen , Charles Boecker , William Black , Michael Gaboury
发明人： Eric Groen , Charles Boecker , William Black , Michael Gaboury
IPC分类号： H03K3/0231 , H03K3/03 , H03K3/354 , H03L7/099 , H03L7/183 , H03B1/00
CPC分类号： H03K3/0322 , H03L7/0995 , H03L7/183
摘要： A ring oscillator with a plurality of delay stages having selectable active loads for selecting an R-C time constant that defines a delay through the delay stage. The ring oscillator oscillation frequency is a function of the selected R-C time constant, a selectable bias level, and the number of delay stages in the ring oscillator. In one embodiment, a MOSFET device gate-to-source capacitance is used with at least one selectable resistive device to form the R-C time constant. In an alternate embodiment, a plurality of parallel coupled resistive devices and parallel coupled capacitive devices are selectively coupled to the active load circuit to set the delay through the delay stage. The resistive devices are formed to be one of a resistor configured MOSFET device and a traditional resistive element. The capacitive devices are formed to be one of a capacitor configure MOSFET device and a traditional capacitive element.

4. 发明申请

US20050057274A1 TX LINE DRIVER WITH COMMON MODE IDLE STATE AND SELECTABLE SLEW RATES 有权
标题翻译： TX线路驱动器，具有通用模式空闲状态和可选择的睡眠速率
公开(公告)号：US20050057274A1
公开(公告)日：2005-03-17
申请号：US10660448
申请日：2003-09-11
申请人： Eric Groen , Charles Boecker , William Black
发明人： Eric Groen , Charles Boecker , William Black
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003 , H03K19/0185 , H04L25/02 , H04L27/10
CPC分类号： H04L25/028 , H03K19/018514 , H03K19/018585 , H04L25/0276 , H04L25/0278 , H04L25/0292 , H04L27/10
摘要： A transmit line driver with selectable slew rates and a common mode idle state comprises a capacitor array of selectable capacitors coupled between a line driver and a pre-driver wherein a slew rate may be selected by the selectable capacitors. A common mode idle state is provided by coupling a selectable switch (MOSFET in the described embodiment) to a mirror device that provides a bias current to the pre-driver wherein, when the bias current is removed by the switch, the pre-driver produces an output signal that is equal to the supply voltage for the circuit. Accordingly, a differential pair of the line driver are both biased on and provide a common mode idle state. The common mode idle state is equal to one half of an output signal magnitude for a logic one.
摘要翻译：具有可选择的转换速率和共模空闲状态的发送线路驱动器包括耦合在线路驱动器和预驱动器之间的可选择电容器的电容器阵列，其中可选择的电容器可以选择转换速率。通过将可选开关（所述实施例中的MOSFET）耦合到向预驱动器提供偏置电流的反射镜装置来提供共模空闲状态，其中当偏置电流被开关去除时，前驱动器产生输出信号等于电路的电源电压。因此，线路驱动器的差分对都被偏置并提供共模空闲状态。共模空闲状态等于逻辑1的输出信号幅度的一半。

5. 发明申请

US20050057280A1 DAC BASED DRIVER WITH SELECTABLE PRE-EMPHASIS SIGNAL LEVELS 有权
标题翻译：基于DAC的驱动器，具有可选择的前置信号电平
公开(公告)号：US20050057280A1
公开(公告)日：2005-03-17
申请号：US10660062
申请日：2003-09-11
申请人： Eric Groen , Charles Boecker , William Black
发明人： Eric Groen , Charles Boecker , William Black
IPC分类号： H04L25/02 , H04L25/52 , H03K19/094
CPC分类号： H04L25/0282 , H04L25/028 , H04L25/0292
摘要： A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.
摘要翻译：具有可选择的预加重和驱动器信号幅度的发射线路驱动器包括用于设置初级电流电平的初级电流驱动器和预加重电流驱动器，其提供与产生的初级电流电平重叠或相加的额外量的电流由主要的当前驱动程序。基于预加重信号逻辑状态，预加重电流具有负幅度或正幅度。第一当前选择模块定义用于在第一电流镜中选择初级电流驱动器输出信号幅度的参考信号，而第二电流选择模块用于定义选择预加重电流驱动器信号的第二参考信号在第二电流镜中的大小。逻辑生成二进制信号到第一和第二电流选择模块以选择当前电平以及预加重信号。

6. 发明申请

US20060006901A1 DAC based driver with selectable pre-emphasis signal levels 有权
标题翻译：基于DAC的驱动器，具有可选的预加重信号电平
公开(公告)号：US20060006901A1
公开(公告)日：2006-01-12
申请号：US11218962
申请日：2005-09-01
申请人： Eric Groen , Charles Boecker , William Black
发明人： Eric Groen , Charles Boecker , William Black
IPC分类号： H03K19/003
CPC分类号： H04L25/0282 , H04L25/028 , H04L25/0292
摘要： A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.
摘要翻译：具有可选择的预加重和驱动器信号幅度的发射线路驱动器包括用于设置初级电流电平的初级电流驱动器和预加重电流驱动器，其提供与产生的初级电流电平重叠或相加的额外量的电流由主要的当前驱动程序。基于预加重信号逻辑状态，预加重电流具有负幅度或正幅度。第一当前选择模块定义用于在第一电流镜中选择初级电流驱动器输出信号幅度的参考信号，而第二电流选择模块用于定义选择预加重电流驱动器信号的第二参考信号在第二电流镜中的大小。逻辑生成二进制信号到第一和第二电流选择模块以选择当前电平以及预加重信号。

7. 发明授权

US08135037B2 Method and apparatus to encode and synchronize a serial interface 有权
标题翻译：串行接口编码和同步的方法和装置
公开(公告)号：US08135037B2
公开(公告)日：2012-03-13
申请号：US12548135
申请日：2009-08-26
申请人： Charles Boecker , Scott Irwin , Matthew Shafer , Eric Groen , Aaron Hoelscher , Andrew Jenkins , David Black
发明人： Charles Boecker , Scott Irwin , Matthew Shafer , Eric Groen , Aaron Hoelscher , Andrew Jenkins , David Black
IPC分类号： H04J3/06 , H03M13/03
CPC分类号： H04L7/10 , G11C7/1006 , H04L25/03866 , H04L25/4904 , H04L25/491
摘要： The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.
摘要翻译：本公开一般涉及在两个或更多个半导体器件之间传送数据的方法和装置。在一个实施例中，一种方法包括使主设备与从设备同步，其中主设备包括半导体设备。同步包括在第一时间通过第一串行接口从主设备发送第一同步标记数据模式，以及响应于发送第一同步标记数据模式，通过主设备上的第二串行接口在第二时间接收第二同步标记数据模式同步标记数据模式。同步还包括至少部分地基于第一时间和第二时间响应于从主设备向从设备发送的请求而主要设备接收到应答的第三次。

8. 发明授权

US07599396B2 Method of encoding and synchronizing a serial interface 有权
标题翻译：串行接口的编码和同步方法
公开(公告)号：US07599396B2
公开(公告)日：2009-10-06
申请号：US11178958
申请日：2005-07-11
申请人： Charles Boecker , Scott Irwin , Matthew Shafer , Eric Groen , Aaron Hoelscher , Andrew Jenkins , David Black
发明人： Charles Boecker , Scott Irwin , Matthew Shafer , Eric Groen , Aaron Hoelscher , Andrew Jenkins , David Black
IPC分类号： H04J3/06
CPC分类号： H04L7/10 , G11C7/1006 , H04L25/03866 , H04L25/4904 , H04L25/491
摘要： The present disclosure is generally directed to a method of communicating data between two or more semiconductor devices. Serial interfaces using the method have a reduction in latency compared to conventional serial interfaces. The method enables features needed for a serial interface, such as limited run lengths and recognizable data boundaries to establish alignment. In addition, a method for synchronizing two or more semiconductor devices through serial interfaces has been presented. This is done by passing a marker data pattern through the system.
摘要翻译：本公开通常涉及在两个或更多个半导体器件之间传送数据的方法。使用该方法的串行接口与常规串行接口相比具有降低的延迟。该方法启用串行接口所需的功能，例如有限的运行长度和可识别的数据边界以建立对齐。此外，已经提出了通过串行接口同步两个或更多个半导体器件的方法。这是通过将标记数据模式传递通过系统来完成的。

9. 发明授权

US07167410B2 Memory system and memory device having a serial interface 有权
标题翻译：具有串行接口的存储器系统和存储器件
公开(公告)号：US07167410B2
公开(公告)日：2007-01-23
申请号：US11114807
申请日：2005-04-26
申请人： Charles Boecker , Scott Irwin , Matthew Shafer , Eric Groen , Aaron Hoelscher , Andrew Jenkins , David Black
发明人： Charles Boecker , Scott Irwin , Matthew Shafer , Eric Groen , Aaron Hoelscher , Andrew Jenkins , David Black
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C2207/107
摘要： A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.
摘要翻译：公开了一种可以包括串行数据接口，串行地址接口和参考时钟接口的存储器件和系统。参考时钟接口被配置为从参考时钟源接收信号，该信号将参考时钟信号提供给存储器控制装置。串行接口耦合到其他存储器设备或存储器控制设备。还公开了使用串行接口在存储器系统内传送数据的方法。该方法包括在参考时钟上执行时钟倍增以提供倍增时钟，使用倍增时钟将数据串行化并传输到串行接口，从密封接口恢复数据，使用参考时钟确定时钟使用的初始频率和数据恢复模块，使用从串行接口恢复的数据来确定恢复的时钟的相位和最终频率，并且使用恢复的时钟将接收到的串行数据解码为并行数据字。

10. 发明申请

US20060239107A1 Memory system and memory device having a serial interface 有权
标题翻译：具有串行接口的存储器系统和存储器件
公开(公告)号：US20060239107A1
公开(公告)日：2006-10-26
申请号：US11114807
申请日：2005-04-26
申请人： Charles Boecker , Scott Irwin , Matthew Shafer , Eric Groen , Aaron Hoelscher , Andrew Jenkins , David Black
发明人： Charles Boecker , Scott Irwin , Matthew Shafer , Eric Groen , Aaron Hoelscher , Andrew Jenkins , David Black
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C2207/107
摘要： A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.
摘要翻译：公开了一种可以包括串行数据接口，串行地址接口和参考时钟接口的存储器件和系统。参考时钟接口被配置为从参考时钟源接收信号，该信号将参考时钟信号提供给存储器控制装置。串行接口耦合到其他存储器设备或存储器控制设备。还公开了使用串行接口在存储器系统内传送数据的方法。该方法包括在参考时钟上执行时钟倍增以提供倍增时钟，使用倍增时钟将数据串行化并传输到串行接口，从密封接口恢复数据，使用参考时钟确定时钟使用的初始频率和数据恢复模块，使用从串行接口恢复的数据来确定恢复的时钟的相位和最终频率，并且使用恢复的时钟将接收到的串行数据解码为并行数据字。

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