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1. 发明授权

US07406118B2 Programmable logic device including programmable multi-gigabit transceivers 有权
标题翻译：可编程逻辑器件包括可编程的多吉比特收发器
公开(公告)号：US07406118B2
公开(公告)日：2008-07-29
申请号：US10661016
申请日：2003-09-11
申请人： Eric D. Groen , Charles W. Boecker , William C. Black , Scott A. Irwin , Joseph N. Kryzak , Yiqin Chen , Andrew G. Jenkins , Aaron J. Hoelscher
发明人： Eric D. Groen , Charles W. Boecker , William C. Black , Scott A. Irwin , Joseph N. Kryzak , Yiqin Chen , Andrew G. Jenkins , Aaron J. Hoelscher
IPC分类号： H04B1/38
CPC分类号： H04L25/14
摘要： A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.
摘要翻译：可编程逻辑器件包括多个可编程的多吉比特收发器，可编程逻辑结构和控制模块。根据多个收发器设置，多个可编程的多吉比特收发器中的每一个被单独编程为期望的收发操作模式。可编程逻辑结构可操作地耦合到多个可编程的多吉比特收发器，并且被配置为处理经由多吉比特收发器收发的数据的至少一部分。控制模块可操作地耦合以基于可编程逻辑器件的期望操作模式产生多个收发器设置。

2. 发明授权

US06976102B1 Integrated circuit with auto negotiation 有权
标题翻译：集成电路与自动协商
公开(公告)号：US06976102B1
公开(公告)日：2005-12-13
申请号：US10660159
申请日：2003-09-11
申请人： Eric D. Groen , Charles W. Boecker , William C. Black , Scott A. Irwin , Joseph N. Kryzak , Aaron J. Hoelscher
发明人： Eric D. Groen , Charles W. Boecker , William C. Black , Scott A. Irwin , Joseph N. Kryzak , Aaron J. Hoelscher
IPC分类号： G06F13/38 , H04L29/06
CPC分类号： H04L69/24 , H04Q2213/13003 , H04Q2213/1305 , H04Q2213/13056 , H04Q2213/13103 , H04Q2213/13109 , H04Q2213/13204 , H04Q2213/1329 , H04Q2213/13297 , H04Q2213/13299 , H04Q2213/1332 , H04Q2213/13322 , H04Q2213/13367
摘要： Method and apparatus for auto-negotiation of a programmable logic device for any of a plurality of communication protocols is described. The programmable logic device is programmed for auto negotiation to establish a communication session. The programmable logic device has access to transceiver attributes. A portion of the transceiver attributes are selected in response to session information from the auto negotiation. The portion of the transceiver attributes selected are for configuring at least one transceiver for a communication protocol.
摘要翻译：描述了用于多个通信协议中的任何一个的可编程逻辑设备的自动协商的方法和装置。可编程逻辑器件被编程用于自动协商以建立通信会话。可编程逻辑器件可以访问收发器属性。响应于来自自动协商的会话信息选择收发器属性的一部分。选择的收发器属性的部分用于为通信协议配置至少一个收发器。

3. 发明授权

US07885320B1 MGT/FPGA clock management system 有权
标题翻译： MGT / FPGA时钟管理系统
公开(公告)号：US07885320B1
公开(公告)日：2011-02-08
申请号：US10660254
申请日：2003-09-11
申请人： Eric D. Groen , Charles W. Boecker , William C. Black , Scott A. Irwin , Joseph Neil Kryzak
发明人： Eric D. Groen , Charles W. Boecker , William C. Black , Scott A. Irwin , Joseph Neil Kryzak
IPC分类号： H04B1/38
CPC分类号： H04J3/0685 , H04L12/40013
摘要： A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream and for providing the recovered clock to a circuit portion, for example, a portion of a field programmable gate array fabric, to enable the circuit portion to use either a reference clock or the recovered clock for subsequent processing. The invention specifically allows for different circuitry portions to utilize different clocks, including different recovered clocks, for corresponding functions that are being performed. Applications for the present invention are many but include multi-gigabit transceiver, switching devices, and protocol translation devices. More generally, the device and method provide for application specific clock references to be utilized in order to minimize or eliminate timing mismatch in serial data processing.
摘要翻译：用于处理高数据速率串行数据的设备和方法包括用于基于高数据速率输入数据流来恢复时钟并用于将恢复的时钟提供给电路部分的电路，例如，现场可编程门阵列结构以使电路部分能够使用参考时钟或恢复的时钟来进行后续处理。本发明具体允许不同的电路部分利用正在执行的相应功能的不同时钟，包括不同的恢复时钟。本发明的应用很多，但包括多千兆收发器，交换设备和协议转换设备。更一般地，该装置和方法提供了应用特定的时钟参考以便使串行数据处理中的时序不匹配最小化或消除。

4. 发明授权

US07493095B2 PMA RX in coarse loop for high speed sampling 有权
标题翻译：用于高速采样的粗环中的PMA RX
公开(公告)号：US07493095B2
公开(公告)日：2009-02-17
申请号：US11796111
申请日：2007-04-25
申请人： Jerry Chuang , William C. Black , Scott A. Irwin
发明人： Jerry Chuang , William C. Black , Scott A. Irwin
IPC分类号： H04B1/06 , H04B1/16
CPC分类号： H03L7/18 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/033
摘要： A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.
摘要翻译：用于处理高数据速率串行数据的设备和方法包括用于基于高数据速率输入数据流来恢复时钟的电路。收发器包括选择性地提供具有在指定量内的精度的时钟的锁相环的粗略回路。在采样操作模式中，只有粗环路PLL被耦合以提供可以从其导出振荡信号和时钟的误差信号。在第二模式（锁定）操作中，收发器可以通过耦合精细环路PLL来提供经调整的误差信号来锁定到接收到的串行数据流。在第三种操作模式中，（自动）收发器最初通过去耦合精细环路PLL并耦合粗环路PLL直到达到稳定状态来执行粗略校准。

5. 发明授权

US08391343B1 PMA RX in coarse loop for high speed sampling 有权
标题翻译：用于高速采样的粗环中的PMA RX
公开(公告)号：US08391343B1
公开(公告)日：2013-03-05
申请号：US12247125
申请日：2008-10-07
申请人： Jerry Chuang , William C. Black , Scott A. Irwin
发明人： Jerry Chuang , William C. Black , Scott A. Irwin
IPC分类号： H04B1/38 , H04L27/00 , H03K9/00
CPC分类号： H03L7/18 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/033
摘要： A high data rate transceiver for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. The transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.
摘要翻译：用于处理高数据速率串行数据的高数据速率收发器包括用于基于高数据速率输入数据流来恢复时钟的电路。收发器包括一个锁相环的粗略回路，其选择性地提供具有在指定量内的精度的时钟。在采样操作模式中，只有粗环路PLL被耦合以提供可以从其导出振荡信号和时钟的误差信号。在第二模式（锁定）操作中，收发器可以通过耦合精细环路PLL来提供经调整的误差信号来锁定到接收到的串行数据流。在第三种操作模式中，（自动）收发器最初通过去耦合精细环路PLL并耦合粗环路PLL直到达到稳定状态来执行粗略校准。

6. 发明授权

US07188283B1 Communication signal testing with a programmable logic device 有权
标题翻译：通信信号测试与可编程逻辑器件
公开(公告)号：US07188283B1
公开(公告)日：2007-03-06
申请号：US10660243
申请日：2003-09-11
申请人： Matthew S. Shafer , Bodhisattva Das , William C. Black , Scott A. Irwin
发明人： Matthew S. Shafer , Bodhisattva Das , William C. Black , Scott A. Irwin
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31715 , G06F11/221 , H04L43/50
摘要： Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.
摘要翻译：描述了用于配置可编程逻辑器件以在信号通道上执行测试的方法和装置。可编程逻辑器件的可配置逻辑被配置为测试模式。可配置互连被配置用于从或从可配置逻辑传送到耦合到可配置输入/输出互连的收发器以从其传送测试信号。

7. 发明授权

US07224951B1 PMA RX in coarse loop for high speed sampling 有权
标题翻译：用于高速采样的粗环中的PMA RX
公开(公告)号：US07224951B1
公开(公告)日：2007-05-29
申请号：US10659966
申请日：2003-09-11
申请人： Jerry Chuang , William C. Black , Scott A. Irwin
发明人： Jerry Chuang , William C. Black , Scott A. Irwin
IPC分类号： H04B1/06 , H04B1/16
CPC分类号： H03L7/18 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/033
摘要： A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.
摘要翻译：用于处理高数据速率串行数据的设备和方法包括用于基于高数据速率输入数据流来恢复时钟的电路。收发器包括选择性地提供具有在指定量内的精度的时钟的锁相环的粗略回路。在采样操作模式中，只有粗环路PLL被耦合以提供可以从其导出振荡信号和时钟的误差信号。在第二模式（锁定）操作中，收发器可以通过耦合精细环路PLL来提供经调整的误差信号来锁定到接收到的串行数据流。在第三种操作模式中，（自动）收发器最初通过去耦合精细环路PLL并耦合粗环路PLL直到达到稳定状态来执行粗略校准。

8. 发明授权

US07213742B1 System and method for value creation 有权
标题翻译：价值创造的系统和方法
公开(公告)号：US07213742B1
公开(公告)日：2007-05-08
申请号：US11011720
申请日：2004-12-14
申请人： Robert D. Birch , Joseph P. Lupo , Scott A. Irwin , Stephen D. Weagraff , Sanjiv Karani , Jeff Gordon
发明人： Robert D. Birch , Joseph P. Lupo , Scott A. Irwin , Stephen D. Weagraff , Sanjiv Karani , Jeff Gordon
IPC分类号： G06F17/00 , G06Q30/00
CPC分类号： G06Q30/06 , G06Q30/0207 , G06Q30/0222 , G06Q30/0226 , G06Q30/0234 , G06Q30/0238 , G06Q40/00
摘要： There is disclosed a system and method for creating value by facilitating third party participation in mobile commerce transactions, providing consumers with a unified perspective of commercial activity, and selectively implementing discounts. The system may include a computerized engine and a point of sale wallet, which may be embedded in a personal trusted device. The computerized engine may be programmed to selectively implement a discount associated with a particular transaction. The personal trusted device may comprise a wireless communications technology, which enables the device to communicate with a back-end system and/or other point of sale devices. The personal trusted device may serve as the nexus of consumer transactions by facilitating payment as well as receipt and storage of electronic receipts. The personal trusted device may also be configured to transmit electronic receipts via the communications technology.
摘要翻译：披露了通过促进第三方参与移动商务交易来创造价值的系统和方法，为消费者提供商业活动的统一视角，并选择性地实施折扣。该系统可以包括可以嵌入在个人信任的设备中的计算机引擎和销售点钱包。计算机化引擎可以被编程为选择性地实现与特定事务相关联的折扣。个人可信设备可以包括无线通信技术，其使设备能够与后端系统和/或其他销售点设备进行通信。个人信任的设备可以通过促进电子收据的支付以及收据和存储来作为消费者交易的纽带。个人可信设备还可以被配置为经由通信技术来发送电子收据。

9. 发明授权

US09135642B1 System and method for device-based eCare 有权
标题翻译：基于设备的eCare的系统和方法
公开(公告)号：US09135642B1
公开(公告)日：2015-09-15
申请号：US12856271
申请日：2010-08-13
申请人： Scott A. Irwin , Robert D. Birch , Joseph P. Lupo , Sanjiv Karani , Stephen D. Weagraff
发明人： Scott A. Irwin , Robert D. Birch , Joseph P. Lupo , Sanjiv Karani , Stephen D. Weagraff
IPC分类号： G06Q30/00 , G06Q30/02
CPC分类号： G06Q30/0256
摘要： There is disclosed a device-based eCare solution that facilitates computerized consumer service on consumer devices. The system may include an end device, a back-end server eCare system, and a communications technology. One or more consumer eCare applications, such as balance and pricing applications, consumer assistance applications, diagnostic applications, and anticipatory applications, may be resident on the device. The end device may be configured to monitor the consumer's activity and collect and store a set of data regarding the consumer's activity. The end device may be further programmed to proactively offer the consumer a consumer eCare application based on the set of data and execute the consumer eCare application in accordance with the consumer's instructions. The system may create a collaborative environment between the device, other devices, and the back-end server eCare system. The device may intermittently communicate with other devices, the back-end server eCare system, or both, to synchronize information.
摘要翻译：披露了一种基于设备的eCare解决方案，可帮助消费者设备上的计算机化消费者服务。该系统可以包括终端设备，后端服务器eCare系统和通信技术。一个或多个消费者eCare应用程序（例如平衡和定价应用程序，消费者援助应用程序，诊断应用程序和预期应用程序）可能驻留在设备上。终端设备可以被配置为监视消费者的活动并且收集和存储关于消费者活动的一组数据。终端设备可以进一步被编程为主动地向消费者提供基于该组数据的消费者eCare应用，并且根据消费者的指令执行消费者eCare应用。该系统可以在设备，其他设备和后端服务器eCare系统之间创建协作环境。设备可以间歇地与其他设备，后端服务器eCare系统或两者进行通信，以同步信息。

10. 发明授权

US08200610B1 System and method for supporting the utilization of machine learning 有权
标题翻译：支持机器学习的系统和方法
公开(公告)号：US08200610B1
公开(公告)日：2012-06-12
申请号：US13236079
申请日：2011-09-19
申请人： Robert D. Birch , Brian D. Craig , Scott A. Irwin , Stephen D. Weagraff
发明人： Robert D. Birch , Brian D. Craig , Scott A. Irwin , Stephen D. Weagraff
IPC分类号： G06F15/00 , G06F15/18
CPC分类号： G06N99/005
摘要： A system and method is disclosed which integrates a machine learning solution into a large scale, distributed transaction processing system using a supporting architecture comprising a combination of computer hardware and software. Methods of using a system comprising such supporting architecture provide application designers access to the functionality included in a machine learning solution, but might also provide additional functionality not supported by the machine learning solution itself.
摘要翻译：公开了一种使用包括计算机硬件和软件的组合的支持架构将机器学习解决方案集成到大规模分布式事务处理系统中的系统和方法。使用包括这种支持架构的系统的方法使应用程序设计人员能够访问包括在机器学习解决方案中的功能，但也可能提供机器学习解决方案本身不支持的附加功能。

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