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1. 发明授权

US06958272B2 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
标题翻译：袖珍种植体用于SONOS存储器单元的互补位干扰改进和充电改进
公开(公告)号：US06958272B2
公开(公告)日：2005-10-25
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
发明人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。然后执行位线注入以在衬底内建立掩埋位线。然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

2. 发明授权

US08957472B2 Memory device having trapezoidal bitlines and method of fabricating same 有权
标题翻译：具有梯形位线的存储器件及其制造方法
公开(公告)号：US08957472B2
公开(公告)日：2015-02-17
申请号：US13357252
申请日：2012-01-24
申请人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。

3. 发明授权

US08125018B2 Memory device having trapezoidal bitlines and method of fabricating same 有权
标题翻译：具有梯形位线的存储器件及其制造方法
公开(公告)号：US08125018B2
公开(公告)日：2012-02-28
申请号：US11033588
申请日：2005-01-12
申请人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。

4. 发明申请

US20120122285A1 MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD FO FABRICATING SAME 有权
标题翻译：具有铁氰酸钾的存储器件及其制造方法
公开(公告)号：US20120122285A1
公开(公告)日：2012-05-17
申请号：US13357252
申请日：2012-01-24
申请人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
IPC分类号： H01L21/336
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。

5. 发明授权

US07414277B1 Memory cell having combination raised source and drain and method of fabricating same 有权
标题翻译：具有组合升高源极和漏极的存储单元及其制造方法
公开(公告)号：US07414277B1
公开(公告)日：2008-08-19
申请号：US11112884
申请日：2005-04-22
申请人： Ashot Melik-Martirosian , Takashi Orimoto , Mark T. Ramsbey
发明人： Ashot Melik-Martirosian , Takashi Orimoto , Mark T. Ramsbey
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储装置包括一对升高的位线，其中位线具有由第一工艺形成的下部分和由第二工序形成的上部部分。

6. 发明授权

US06927145B1 Bitline hard mask spacer flow for memory cell scaling 有权
标题翻译：位线硬掩模间隔流程用于存储单元缩放
公开(公告)号：US06927145B1
公开(公告)日：2005-08-09
申请号：US10770673
申请日：2004-02-02
申请人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
发明人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
IPC分类号： H01L21/027 , H01L21/761 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和形成半导体器件的方法。半导体器件包括衬底; 在衬底中形成的掩埋位线比在光刻的分辨率极限下可实现的更窄; 与所述掩埋位线中的至少一个相邻地形成的掺杂区域; 设置在所述基板上的电荷捕获层; 以及设置在所述电荷俘获层上的导电层，其中与所述掩埋位线中的至少一个相邻的所述掺杂区域抑制所述掩埋位线之间的漏电流。

7. 发明授权

US6001713A Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device 有权
标题翻译：在非易失性半导体存储器件中的浮栅和互聚电介质层中形成富氮区的方法
公开(公告)号：US6001713A
公开(公告)日：1999-12-14
申请号：US154074
申请日：1998-09-16
申请人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
发明人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
IPC分类号： H01L21/28 , H01L21/265
CPC分类号： H01L21/28273
摘要： Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.
摘要翻译：提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。这在浮动栅极内形成初始氮浓度分布。然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

8. 发明授权

US06642573B1 Use of high-K dielectric material in modified ONO structure for semiconductor devices 有权
标题翻译：在改性ONO结构中使用高K介电材料用于半导体器件
公开(公告)号：US06642573B1
公开(公告)日：2003-11-04
申请号：US10097912
申请日：2002-03-13
申请人： Arvind Halliyal , Mark T. Ramsbey , Wei Zhang , Mark W. Randolph , Fred T. K. Cheung
发明人： Arvind Halliyal , Mark T. Ramsbey , Wei Zhang , Mark W. Randolph , Fred T. K. Cheung
IPC分类号： H01L29788
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28273 , H01L21/28282 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31691 , H01L21/3185 , H01L28/56 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/518 , Y10S438/954
摘要： A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first dielectric material layer on the semiconductor substrate; depositing a silicon nitride layer on the first dielectric material layer; and forming a top dielectric material layer, wherein at least one of the bottom dielectric material layer and the top dielectric material layer comprise a mid-K or a high-K dielectric material. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate flash device including the modified ONO structure.
摘要翻译：一种制造包括修饰的ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一介电材料层; 在第一介电材料层上沉积氮化硅层; 以及形成顶部介电材料层，其中所述底部电介质材料层和所述顶部电介质材料层中的至少一个包括中间K或高K电介质材料。半导体器件可以是例如SONOS两位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。

9. 发明授权

US06639271B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 失效
标题翻译：用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法
公开(公告)号：US06639271B1
公开(公告)日：2003-10-28
申请号：US10027253
申请日：2001-12-20
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L29792
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
摘要翻译：在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

10. 发明授权

US07001807B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
公开(公告)号：US07001807B1
公开(公告)日：2006-02-21
申请号：US10997345
申请日：2004-11-24
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/512 , H01L29/517 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

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