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1. 发明申请

US20100157718A1 Configurable Latching for Asynchronous Memories 有权
标题翻译：可配置的异步存储器锁存
公开(公告)号：US20100157718A1
公开(公告)日：2010-06-24
申请号：US12342342
申请日：2008-12-23
申请人： Emanuele Confalonieri , Daniele Balluchi , Chris Bueb , Graziano Mirichigini
发明人： Emanuele Confalonieri , Daniele Balluchi , Chris Bueb , Graziano Mirichigini
IPC分类号： G11C8/18
CPC分类号： G11C7/1027 , G11C7/1045
摘要： A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller's techniques for entering synchronous burst read mode. In some embodiments, the bit may selectively enable the memory to assume one of two synchronous burst read modes which are based on different arrangements of CLK and ADV# signals.
摘要翻译：诸如闪存的存储器可以从存储器控制器接收配置位，以将存储器设置为两种可选模式之一。因此，基于存储器控制器的操作方式，它可以适应存储器的操作以适应用于进入同步突发读取模式的存储器控制器的技术。在一些实施例中，该位可以选择性地使存储器能够采用基于CLK和ADV＃信号的不同布置的两个同步脉冲串读取模式之一。

2. 发明授权

US08762656B2 Temperature alert and low rate refresh for a non-volatile memory 有权
标题翻译：非易失性存储器的温度警报和低速刷新
公开(公告)号：US08762656B2
公开(公告)日：2014-06-24
申请号：US13142418
申请日：2008-12-30
申请人： Emanuele Confalonieri , Daniele Balluchi
发明人： Emanuele Confalonieri , Daniele Balluchi
IPC分类号： G06F13/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0033 , G11C16/3431
摘要： A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the temperature alert is active, and in response to the determination that the temperature alert is active, refreshing at least a portion of the non-volatile memory.
摘要翻译：描述了一种用于测量非易失性存储器内的温度的方法和装置，其在非易失性存储器内的寄存器中存储包括指示非易失性存储器的一个或多个位的温度警报已超过阈值温度时间段，由主机确定温度警报是活动的，并且响应于温度警报激活的确定，刷新至少一部分非易失性存储器。

3. 发明申请

US20120033519A1 TEMPERATURE ALERT AND LOW RATE REFRESH FOR A NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的温度警报和低速刷新
公开(公告)号：US20120033519A1
公开(公告)日：2012-02-09
申请号：US13142418
申请日：2008-12-30
申请人： Emanuele Confalonieri , Daniele Balluchi
发明人： Emanuele Confalonieri , Daniele Balluchi
IPC分类号： G11C11/402
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0033 , G11C16/3431
摘要： A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the temperature alert is active, and in response to the determination that the temperature alert is active, refreshing at least a portion of the non-volatile memory.
摘要翻译：描述了一种用于测量非易失性存储器内的温度的方法和装置，其在非易失性存储器内的寄存器中存储包括指示非易失性存储器的一个或多个位的温度警报已超过阈值温度时间段，由主机确定温度警报是活动的，并且响应于温度警报激活的确定，刷新至少一部分非易失性存储器。

4. 发明授权

US07916575B2 Configurable latching for asynchronous memories 有权
标题翻译：用于异步存储器的可配置锁存
公开(公告)号：US07916575B2
公开(公告)日：2011-03-29
申请号：US12342342
申请日：2008-12-23
申请人： Emanuele Confalonieri , Daniele Balluchi , Chris Bueb , Graziano Mirichigni
发明人： Emanuele Confalonieri , Daniele Balluchi , Chris Bueb , Graziano Mirichigni
IPC分类号： G11C8/00
CPC分类号： G11C7/1027 , G11C7/1045
摘要： A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller's techniques for entering synchronous burst read mode. In some embodiments, the bit may selectively enable the memory to assume one of two synchronous burst read modes which are based on different arrangements of CLK and ADV# signals.
摘要翻译：诸如闪存的存储器可以从存储器控制器接收配置位，以将存储器设置为两种可选模式之一。因此，基于存储器控制器的操作方式，它可以适应存储器的操作以适应用于进入同步突发读取模式的存储器控制器的技术。在一些实施例中，该位可以选择性地使存储器能够采用基于CLK和ADV＃信号的不同布置的两个同步脉冲串读取模式之一。

5. 发明申请

US20100306446A1 METHOD AND DEVICES FOR CONTROLLING POWER LOSS 有权
标题翻译：用于控制电力损失的方法和装置
公开(公告)号：US20100306446A1
公开(公告)日：2010-12-02
申请号：US12472153
申请日：2009-05-26
申请人： Corrado Villa , Daniele Balluchi , Graziano Mirichigni
发明人： Corrado Villa , Daniele Balluchi , Graziano Mirichigni
IPC分类号： G06F12/16 , G06F1/00
CPC分类号： G11C5/14 , G06F1/30 , G11C5/144
摘要： Described herein are methods and devices for controlling power loss. For one embodiment, a method includes issuing a controlled power off command with a controller. The method includes determining whether a memory device is performing a background operation. The method includes safely suspending the background operation or completing the background operation if the memory device is performing the background operation. The method includes safely removing a supply power.
摘要翻译：这里描述了用于控制功率损耗的方法和装置。对于一个实施例，一种方法包括用控制器发出受控断电命令。该方法包括确定存储器件是否正在执行后台操作。该方法包括：如果存储器件正在执行后台操作，则安全地挂起后台操作或完成后台操作。该方法包括安全地去除电源。

6. 发明授权

US06507534B2 Column decoder circuit for page reading of a semiconductor memory 有权
标题翻译：用于半导体存储器的页面读取的列解码器电路
公开(公告)号：US06507534B2
公开(公告)日：2003-01-14
申请号：US09797171
申请日：2001-02-27
申请人： Daniele Balluchi
发明人： Daniele Balluchi
IPC分类号： G11C700
CPC分类号： G11C7/1021 , G11C8/10
摘要： A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage, a second level decoder stage, and a plurality of bit selection stages, each comprising a plurality of selection branches; wherein each selection branch is connected to a respective input of a multiplexer and has a plurality of first level selector stages and a second level selector stage. Each second level selector stage comprises a first addressing selector for addressing a first group of bit lines. Each bit selection stage further comprises a second addressing selector for addressing a second group of bit lines, current and next page selectors for selecting one of the first and second groups of bit lines.
摘要翻译：用于半导体存储器的页面读取的列解码器电路包括：第一电平解码器级，第二级解码器级和多个位选择级，每级包括多个选择分支; 其中每个选择分支连接到多路复用器的相应输入端，并且具有多个第一电平选择器级和第二电平选择器级。每个第二级选择器级包括用于寻址第一组位线的第一寻址选择器。每个比特选择阶段还包括用于寻址第二组位线的第二寻址选择器，用于选择第一组和第二组位线之一的当前和下一页选择器。

7. 发明申请

US20120314522A1 CONTROLLING CLOCK INPUT BUFFERS 有权
标题翻译：控制时钟输入缓冲器
公开(公告)号：US20120314522A1
公开(公告)日：2012-12-13
申请号：US13519846
申请日：2009-12-30
申请人： Daniele Balluchi , Daniele Vimercati , Graziano Mirichigni
发明人： Daniele Balluchi , Daniele Vimercati , Graziano Mirichigni
IPC分类号： G11C5/14 , H03K3/00
CPC分类号： H03K3/012 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4072
摘要： An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up.
摘要翻译：集成电路可以具有耦合到缓冲器（24）的时钟输入引脚。缓冲器可以向诸如存储器的集成电路芯片提供时钟信号（28）。为了节省电力，缓冲区掉电。当准备使用时，缓冲区被快速备份。在一个实施例中，响应于预定数量的时钟信号切换，缓冲器被自动加电。

8. 发明授权

US07154803B2 Redundancy scheme for a memory integrated circuit 有权
标题翻译：存储器集成电路的冗余方案
公开(公告)号：US07154803B2
公开(公告)日：2006-12-26
申请号：US10893760
申请日：2004-07-16
申请人： Andrea Martinelli , Daniele Balluchi , Corrado Villa
发明人： Andrea Martinelli , Daniele Balluchi , Corrado Villa
IPC分类号： G11C8/00
CPC分类号： G11C29/83
摘要： A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address. The redundancy scheme comprises at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line. A memory sector unusable status indicator element is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.
摘要翻译：一种用于具有至少两个存储器扇区并且与每个存储器扇区相关联的存储器集成电路的冗余方案，相应的存储器位置选择器用于根据地址选择存储器扇区内的存储器位置。所述冗余方案包括至少一个适于功能地替代所述至少两个存储器扇区中的一个的冗余存储器扇区，以及冗余控制电路，用于使所述至少一个冗余存储器中的一个被声明为无法使用的存储器扇区的功能替换部门冗余控制电路检测对不可用存储器扇区内的存储器位置的访问请求，并将访问请求转发到冗余存储器扇区中的相应冗余存储器位置。与每个存储器位置选择器相关联，提供相应的电源控制装置，其适于选择性地将相关联的存储器位置选择器连接/断开与电源分配线的连接/断开。存储器部分不可用状态指示器元件与每个存储器扇区相关联，用于控制相应的电源控制装置，以便在设置时引起各个存储器位置选择器与电源分配线的选择性断开。

9. 发明授权

US08543787B2 Non-volatile memory circuit, system, and method 有权
标题翻译：非易失性存储器电路，系统和方法
公开(公告)号：US08543787B2
公开(公告)日：2013-09-24
申请号：US12148521
申请日：2008-04-17
申请人： Daniele Balluchi , Graziano Mirichigni
发明人： Daniele Balluchi , Graziano Mirichigni
IPC分类号： G06F12/00
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0685 , G06F12/0638 , G06F2212/2022 , G11C7/1015 , G11C7/1078 , G11C7/1084 , G11C16/102 , G11C16/32 , Y02D10/13
摘要： A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.
摘要翻译：非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。

10. 发明申请

US20050047226A1 Redundancy scheme for a memory integrated circuit 有权
标题翻译：存储器集成电路的冗余方案
公开(公告)号：US20050047226A1
公开(公告)日：2005-03-03
申请号：US10893760
申请日：2004-07-16
申请人： Andrea Martinelli , Daniele Balluchi , Corrado Villa
发明人： Andrea Martinelli , Daniele Balluchi , Corrado Villa
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/83
摘要： A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address. The redundancy scheme comprises at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line. A memory sector unusable status indicator element is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.
摘要翻译：一种用于具有至少两个存储器扇区并且与每个存储器扇区相关联的存储器集成电路的冗余方案，相应的存储器位置选择器用于根据地址选择存储器扇区内的存储器位置。所述冗余方案包括至少一个适于功能地替代所述至少两个存储器扇区中的一个的冗余存储器扇区，以及冗余控制电路，用于使所述至少一个冗余存储器中的一个被声明为无法使用的存储器扇区的功能替换部门冗余控制电路检测对不可用存储器扇区内的存储器位置的访问请求，并将访问请求转发到冗余存储器扇区中的相应冗余存储器位置。与每个存储器位置选择器相关联，提供相应的电源控制装置，其适于选择性地将相关联的存储器位置选择器连接/断开与电源分配线的连接/断开。存储器部分不可用状态指示器元件与每个存储器扇区相关联，用于控制相应的电源控制装置，以便在设置时引起各个存储器位置选择器与电源分配线的选择性断开。

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