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1. 发明授权

US5815699A Configurable branch prediction for a processor performing speculative execution 失效
公开(公告)号：US5815699A
公开(公告)日：1998-09-29
申请号：US472698
申请日：1995-06-06
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

2. 发明授权

US06671798B1 Configurable branch prediction for a processor performing speculative execution 失效
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06671798B1
公开(公告)日：2003-12-30
申请号：US09992822
申请日：2001-11-16
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。该配置可以通过软件进行编程。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一个状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

3. 发明授权

US06360318B1 Configurable branch prediction for a processor performing speculative execution 失效
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06360318B1
公开(公告)日：2002-03-19
申请号：US09608451
申请日：2000-06-29
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically In software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。可以通过编程方式在软件中完成配置。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一个状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

4. 发明授权

US06282639B1 Configurable branch prediction for a processor performing speculative execution 有权
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06282639B1
公开(公告)日：2001-08-28
申请号：US09608448
申请日：2000-06-29
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F900
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss Information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。该配置可以通过软件进行编程。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

5. 发明授权

US6108777A Configurable branch prediction for a processor performing speculative execution 失效
公开(公告)号：US6108777A
公开(公告)日：2000-08-22
申请号：US73499
申请日：1998-05-06
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

6. 发明授权

US06633945B1 Fully connected cache coherent multiprocessing systems 有权
标题翻译：完全连接的缓存一致多处理系统
公开(公告)号：US06633945B1
公开(公告)日：2003-10-14
申请号：US09349641
申请日：1999-07-08
申请人： Daniel Fu , Carlton T. Amdahl , Walstein Bennett Smith, III
发明人： Daniel Fu , Carlton T. Amdahl , Walstein Bennett Smith, III
IPC分类号： G06F1300
CPC分类号： G06F12/0813 , G06F12/0822 , G06F15/17375
摘要： Fully connected multiple FCU-based architectures reduce requirements for Tag SRAM size and memory read latencies. A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems.
摘要翻译：完全连接的多个基于FCU的架构降低了标签SRAM大小和内存读取延迟的要求。对称多处理器系统的优选实施例包括用于数据传输的交换结构（交换矩阵），其提供多个并行总线，其能够在处理器和共享存储器之间大大增加带宽。高速点对点通道将命令启动器和存储器与开关矩阵和I / O子系统耦合起来。

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