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1. 发明授权

US07244658B2 Low stress STI films and methods 有权
公开(公告)号：US07244658B2
公开(公告)日：2007-07-17
申请号：US11252400
申请日：2005-10-17
申请人： Ellie Y Yieh , Lung-Tien Han , Anchuan Wang , Lin Zhang
发明人： Ellie Y Yieh , Lung-Tien Han , Anchuan Wang , Lin Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , C23C16/045 , C23C16/401 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02274 , H01L21/31625 , H01L21/31629
摘要： The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less than 180 MPa, and preferably less than about 170 MPa. In certain embodiment, the STI films of the invention will exhibit a compressive stress less than about 100 MPa. Further, in certain embodiments, the low compressive stress STI films of the invention will comprise between about 0.1 and 25 atomic % of the stress-lowering dopant.

2. 发明授权

US07524750B2 Integrated process modulation (IPM) a novel solution for gapfill with HDP-CVD 失效
标题翻译：集成过程调制（IPM）是HDP-CVD填缝的新解决方案
公开(公告)号：US07524750B2
公开(公告)日：2009-04-28
申请号：US11553772
申请日：2006-10-27
申请人： Srinivas D. Nemani , Young S. Lee , Ellie Y. Yieh , Anchuan Wang , Jason Thomas Bloking , Lung-Tien Han
发明人： Srinivas D. Nemani , Young S. Lee , Ellie Y. Yieh , Anchuan Wang , Jason Thomas Bloking , Lung-Tien Han
IPC分类号： H01L21/20
CPC分类号： H01L21/76224
摘要： A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.
摘要翻译：提供了一种在设置在处理室中的衬底上沉积氧化硅膜的工艺。包括卤素源，流动气体，硅源和氧化性气体反应物的处理气体流入处理室。从处理气体形成具有至少1011个离子/ cm 3的离子密度的等离子体。氧化硅膜以低于1.0％的卤素浓度沉积在衬底上。使用具有同时沉积和溅射组分的工艺，用等离子体沉积氧化硅膜。卤素源到处理室的流速与硅源到处理室的流速基本上在0.5和3.0之间。

3. 发明申请

US20070243693A1 INTEGRATED PROCESS MODULATION (IPM) A NOVEL SOLUTION FOR GAPFILL WITH HDP-CVD 失效
标题翻译：集成过程调制（IPM）用于HDP-CVD的GAPFILL的新颖解决方案
公开(公告)号：US20070243693A1
公开(公告)日：2007-10-18
申请号：US11553772
申请日：2006-10-27
申请人： Srinivas D. Nemani , Young S. Lee , Ellie Y. Yieh , Anchuan Wang , Jason Thomas Bloking , Lung-Tien Han
发明人： Srinivas D. Nemani , Young S. Lee , Ellie Y. Yieh , Anchuan Wang , Jason Thomas Bloking , Lung-Tien Han
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.
摘要翻译：提供了一种在设置在处理室中的衬底上沉积氧化硅膜的工艺。包括卤素源，流动气体，硅源和氧化性气体反应物的处理气体流入处理室。从处理气体形成离子密度为至少10 11个/ cm 3的等离子体。氧化硅膜以低于1.0％的卤素浓度沉积在衬底上。使用具有同时沉积和溅射组分的工艺，用等离子体沉积氧化硅膜。卤素源到处理室的流速与硅源到处理室的流速基本上在0.5和3.0之间。

4. 发明申请

US20070087515A1 Low stress STI films and methods 有权
标题翻译：低应力STI膜和方法
公开(公告)号：US20070087515A1
公开(公告)日：2007-04-19
申请号：US11252400
申请日：2005-10-17
申请人： Ellie Yieh , Lung-Tien Han , Anchuan Wang , Lin Zhang
发明人： Ellie Yieh , Lung-Tien Han , Anchuan Wang , Lin Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , C23C16/045 , C23C16/401 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02274 , H01L21/31625 , H01L21/31629
摘要： The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less than 180 MPa, and preferably less than about 170 MPa. In certain embodiment, the STI films of the invention will exhibit a compressive stress less than about 100 MPa. Further, in certain embodiments, the low compressive stress STI films of the invention will comprise between about 0.1 and 25 atomic % of the stress-lowering dopant.
摘要翻译：本发明一般涉及用于STI应用的低压应力掺杂硅酸盐玻璃膜。作为非限制性实例，应力降低掺杂剂可以是氟掺杂剂，锗掺杂剂或磷掺杂剂。低压应力STI膜通常表现出小于180MPa，优选小于约170MPa的压缩应力。在某些实施方案中，本发明的STI膜将表现出小于约100MPa的压缩应力。此外，在某些实施方案中，本发明的低压应力STI膜将包含应力降低掺杂剂的约0.1至25原子％。

5. 发明申请

US20080142483A1 MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS 审中-公开
标题翻译：多级DEP-ETCH-DEP高密度等离子体化学气相沉积工艺用于电介质
公开(公告)号：US20080142483A1
公开(公告)日：2008-06-19
申请号：US11947619
申请日：2007-11-29
申请人： Zhong Qiang Hua , Rionard Purnawan , Jason Thomas Bloking , Anchuan Wang , Young S. Lee , Ellie Y. Yieh
发明人： Zhong Qiang Hua , Rionard Purnawan , Jason Thomas Bloking , Anchuan Wang , Young S. Lee , Ellie Y. Yieh
IPC分类号： B44C1/22
CPC分类号： C23C16/401 , C23C16/045 , H01L21/02164 , H01L21/02274 , H01L21/31111 , H01L21/3145 , H01L21/31612
摘要： A method of forming a dielectric material in a substrate gap using a high-density plasma is described. The method may include depositing a first portion of the dielectric material into the gap with the high-density plasma. The deposition may form a protruding structure that at least partially blocks the deposition of the dielectric material into the gap. The first portion of dielectric material is exposed to an etchant that includes reactive species from a mixture that includes NH3 and NF3. The etchant forms a solid reaction product with the protruding structure, and the solid reaction product may be removed from the substrate. A final portion of the dielectric material may be deposited in the gap with the high-density plasma.
摘要翻译：描述了使用高密度等离子体在衬底间隙中形成电介质材料的方法。该方法可以包括将电介质材料的第一部分沉积到具有高密度等离子体的间隙中。沉积可以形成至少部分地阻挡介电材料沉积到间隙中的突出结构。电介质材料的第一部分暴露于包括来自包括NH 3和N N 3 3的混合物的反应物质的蚀刻剂。蚀刻剂形成具有突出结构的固体反应产物，并且固体反应产物可以从基底上除去。介电材料的最终部分可以与高密度等离子体在间隙中沉积。

6. 发明授权

US06890597B2 HDP-CVD uniformity control 失效
标题翻译： HDP-CVD均匀性控制
公开(公告)号：US06890597B2
公开(公告)日：2005-05-10
申请号：US10435296
申请日：2003-05-09
申请人： Padmanabhan Krishnaraj , Bruno Geoffrion , Michael S. Cox , Lin Zhang , Bikram Kapoor , Anchuan Wang , Zhenjiang Cui
发明人： Padmanabhan Krishnaraj , Bruno Geoffrion , Michael S. Cox , Lin Zhang , Bikram Kapoor , Anchuan Wang , Zhenjiang Cui
IPC分类号： C23C16/44 , C23C16/455 , C23C16/56 , C23C16/40
CPC分类号： C23C16/45502 , C23C16/45591 , C23C16/56
摘要： A combination of deposition and polishing steps are used to permit improved uniformity of a film after the combination of steps. Both the deposition and polishing are performed with processes that vary across the substrate. The combination of the varying deposition and etching rates results in a film that is substantially planar after the film has been polished. In some instances, it may be easier to control the variation of one of the two processes than the other so that the more controllable process is tailored to accommodate nonuniformities introduced by the less controllable process.
摘要翻译：沉积和抛光步骤的组合用于在步骤组合之后改进膜的均匀性。通过在衬底上变化的工艺来进行沉积和抛光。不同沉积和蚀刻速率的组合导致在膜被抛光之后基本上是平面的膜。在一些情况下，控制两个过程之一的变化比另一个更容易，因此可控制过程被调整以适应由较不可控过程引入的不均匀性。

7. 发明授权

US08999856B2 Methods for etch of sin films 有权
标题翻译：蚀刻薄膜的方法
公开(公告)号：US08999856B2
公开(公告)日：2015-04-07
申请号：US13416277
申请日：2012-03-09
申请人： Jingchun Zhang , Anchuan Wang , Nitin Ingle
发明人： Jingchun Zhang , Anchuan Wang , Nitin Ingle
IPC分类号： H01L21/302 , H01L21/311 , H01J37/32
CPC分类号： H01L21/31116 , C09K13/00 , H01J37/32357 , H01J37/32422 , H01L21/02164 , H01L21/0217 , H01L21/3065 , H01L21/311 , H01L21/32135 , H01L21/32136 , H01L21/32137 , H01L21/67069
摘要： A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.
摘要翻译：从包括氮化硅层和氧化硅层的衬底中选择性地蚀刻氮化硅的方法包括将含氟气体流入衬底处理室的等离子体产生区域并向含氟气体施加能量以产生等离子体在等离子体产生区域中。等离子体包括氟自由基和氟离子。该方法还包括过滤等离子体以提供具有比氟离子更高浓度的氟自由基的反应气体，并使反应气体流入基板处理室的气体反应区域。该方法还包括将衬底暴露于衬底处理室的气体反应区域中的反应气体。反应气体以比反应气体更高的蚀刻速率蚀刻氮化硅层蚀刻氧化硅层。

8. 发明申请

US20130034968A1 DRY-ETCH FOR SILICON-AND-CARBON-CONTAINING FILMS 有权
标题翻译：含硅和碳膜的干燥剂
公开(公告)号：US20130034968A1
公开(公告)日：2013-02-07
申请号：US13279998
申请日：2011-10-24
申请人： Jingchun Zhang , Anchuan Wang , Nitin K. Ingle , Yunyu Wang , Young Lee
发明人： Jingchun Zhang , Anchuan Wang , Nitin K. Ingle , Yunyu Wang , Young Lee
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01L21/31116
摘要： A method of etching exposed silicon-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-carbon-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-carbon-containing material from the exposed silicon-and-carbon-containing material regions while very slowly removing other exposed materials. The silicon-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate. The methods may be used to selectively remove silicon-and-carbon-containing material at more than twenty times the rate of silicon oxide.
摘要翻译：描述了在图案化的异质结构上蚀刻暴露的含硅和碳的材料的方法，并且包括由含氟前体和含氧前体形成的远程等离子体蚀刻。来自远程等离子体的等离子体流出物流入衬底处理区域，其中等离子体流出物与含硅和碳的材料的暴露区域反应。等离子体流出物与图案化的异质结构反应，以便从暴露的含硅和碳的材料区域选择性地除去含硅和碳的材料，同时非常缓慢地除去其它暴露的材料。含硅和碳的材料选择性部分取决于位于远程等离子体和基板处理区域之间的离子抑制元件的存在。离子抑制元件减少或基本消除了到达衬底的离子充电物质的数量。该方法可用于以超过二氧化硅的二十倍的速率选择性地除去含硅和碳的材料。

9. 发明申请

US20100099236A1 GAPFILL IMPROVEMENT WITH LOW ETCH RATE DIELECTRIC LINERS 有权
标题翻译： GAPFILL改进与低调速电介质线
公开(公告)号：US20100099236A1
公开(公告)日：2010-04-22
申请号：US12437256
申请日：2009-05-07
申请人： Young Soo Kwon , Bi Jang , Anchuan Wang , Young S. Lee , Mihaela Balseanu , Li-Qun Xia , Jin Ho Jeon
发明人： Young Soo Kwon , Bi Jang , Anchuan Wang , Young S. Lee , Mihaela Balseanu , Li-Qun Xia , Jin Ho Jeon
IPC分类号： H01L21/762 , H01L21/31
CPC分类号： H01L21/76224 , H01L21/02112 , H01L21/02247 , H01L21/02304 , H01L21/318
摘要： A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.
摘要翻译：描述了填充沟槽的方法，并且包括在含氟蚀刻化学中沉积具有高比率的氧化硅与介电衬里蚀刻速率的介电衬垫。氧化硅沉积在沟槽内并蚀刻以重新打开或加宽沟槽顶部附近的间隙。电介质衬垫在蚀刻工艺期间保护下面的衬底，从而可以使间隙更宽。氧化硅再次沉积在沟槽内以基本上填充沟槽。

10. 发明申请

US20100041207A1 HIGH DENSITY PLASMA GAPFILL DEPOSITION-ETCH-DEPOSITION PROCESS USING FLUOROCARBON ETCHANT 失效
标题翻译：使用荧光探针的高密度等离子体吸附沉积 - 沉积沉积工艺
公开(公告)号：US20100041207A1
公开(公告)日：2010-02-18
申请号：US12193162
申请日：2008-08-18
申请人： Young S. Lee , Ying Rui , Dmitry Lubomirsky , Daniel J. Hoffman , Jang Gyoo Yang , Anchuan Wang
发明人： Young S. Lee , Ying Rui , Dmitry Lubomirsky , Daniel J. Hoffman , Jang Gyoo Yang , Anchuan Wang
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , C23C16/045 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/31116 , H01L21/31612
摘要： A high density plasma dep/etch/dep method of depositing a dielectric film into a gap between adjacent raised structures on a substrate disposed in a substrate processing chamber. The method deposits a first portion of the dielectric film within the gap by forming a high density plasma from a first gaseous mixture flown into the process chamber, etches the deposited first portion of the dielectric film by flowing an etchant gas comprising CxFy, where a ratio of x to y is greater than or equal to 1:2 and then deposits a second portion of the dielectric film over the first portion by forming a high density plasma from a second gaseous mixture flown into the process chamber.
摘要翻译：将介电膜沉积在设置在基板处理室中的基板上的相邻凸起结构之间的间隙中的高密度等离子体蚀刻/蚀刻/蚀刻方法。该方法通过从流入处理室的第一气体混合物形成高密度等离子体，将电介质膜的第一部分沉积在间隙内，通过流过包含CxFy的蚀刻剂气体来蚀刻沉积的电介质膜的第一部分，的x至y大于或等于1：2，然后通过从流入处理室的第二气态混合物形成高密度等离子体，将第二部分电介质膜沉积在第一部分上。

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