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1. 发明授权

US5548553A Method and apparatus for providing high-speed column redundancy 失效
标题翻译：提供高速列冗余的方法和装置
公开(公告)号：US5548553A
公开(公告)日：1996-08-20
申请号：US353603
申请日：1994-12-12
申请人： Elizabeth M. Cooper , Michael Leary
发明人： Elizabeth M. Cooper , Michael Leary
IPC分类号： G11C29/00 , G11C13/00
CPC分类号： G11C29/80 , G11C29/802 , G11C29/848
摘要： A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and at least one redundant column. Each column of the memory sub-array also includes multiplexing means, coupled to the input and output path of the respective column and an input and output path of a neighboring column. In addition, the redundant column is coupled to the input and output path of a neighboring column. In the event that one of the columns of the memory sub-array is defective, the multiplexing means of each of the columns between the defective column and the redundant column acts to couple the input and output paths of that column to the input and output paths of the neighboring column. With such an arrangement, the defective column is bypassed and a memory device capable of operating without defects is provided.
摘要翻译：根据本发明的半导体存储器件包括具有多个存储器子阵列的主存储器阵列。每个存储器子阵列包括多个列和至少一个冗余列。存储器子阵列的每列还包括耦合到相应列的输入和输出路径以及相邻列的输入和输出路径的多路复用装置。此外，冗余列耦合到相邻列的输入和输出路径。在存储器子阵列中的一列存在缺陷的情况下，缺陷列和冗余列之间的每列的复用装置用于将该列的输入和输出路径耦合到输入和输出路径的相邻列。通过这种布置，旁路缺陷列，并且提供能够无缺陷地运行的存储器件。

2. 发明申请

US20130159780A1 CORRELATING TRACES IN A COMPUTING SYSTEM 有权
标题翻译：计算系统中的相关跟踪
公开(公告)号：US20130159780A1
公开(公告)日：2013-06-20
申请号：US13328512
申请日：2011-12-16
申请人： Ryan D. Bedwell , Elizabeth M. Cooper , Eric M. Rentschler
发明人： Ryan D. Bedwell , Elizabeth M. Cooper , Eric M. Rentschler
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/3419 , G06F11/348 , G06F2201/835 , G06F2201/88
摘要： An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.
摘要翻译：用于同步跟踪数据的装置，处理器和方法。处理器包括多个核心，并且每个核心以不同的本地时钟频率运行。全局时钟分配给每个核心，并使用全局时钟和本地时钟生成时间戳。时间戳和本地时钟饱和值包含在每个跟踪条目中，本地时钟饱和值等于本地时钟与全局时钟之间的比率。基于时间戳和本地时钟饱和度值，来自独立核心的跟踪条目在后处理阶段是时间相关的。

3. 发明授权

US08935574B2 Correlating traces in a computing system 有权
标题翻译：计算系统中的相关跟踪
公开(公告)号：US08935574B2
公开(公告)日：2015-01-13
申请号：US13328512
申请日：2011-12-16
申请人： Ryan D. Bedwell , Elizabeth M. Cooper , Eric M. Rentschler
发明人： Ryan D. Bedwell , Elizabeth M. Cooper , Eric M. Rentschler
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F11/3419 , G06F11/348 , G06F2201/835 , G06F2201/88
摘要： An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.
摘要翻译：用于同步跟踪数据的装置，处理器和方法。处理器包括多个核心，并且每个核心以不同的本地时钟频率运行。全局时钟分配给每个核心，并使用全局时钟和本地时钟生成时间戳。时间戳和本地时钟饱和值包含在每个跟踪条目中，本地时钟饱和值等于本地时钟与全局时钟之间的比率。基于时间戳和本地时钟饱和度值，来自独立核心的跟踪条目在后处理阶段是时间相关的。

4. 发明授权

US08683265B2 Debug state machine cross triggering 有权
标题翻译：调试状态机交叉触发
公开(公告)号：US08683265B2
公开(公告)日：2014-03-25
申请号：US12980842
申请日：2010-12-29
申请人： Eric M. Rentschler , Steven J. Kommrusch , Elizabeth M. Cooper , Stephen Ennis
发明人： Eric M. Rentschler , Steven J. Kommrusch , Elizabeth M. Cooper , Stephen Ennis
IPC分类号： G06F11/00
CPC分类号： G06F11/3632 , G01R31/31705 , G06F11/3656
摘要： An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.
摘要翻译：电子系统的实施例包括第一电子模块，第二电子模块，与第一电子模块集成的第一调试电路，与第二电子模块集成的第二调试电路，以及第一调试电路和第二调试电路之间的通信接口第二调试电路。第一调试电路被配置为响应于确定触发事件已经发生而确定触发事件已经发生，并且在通信接口上产生第一交叉触发信号。第二调试电路被配置为检测通信接口上的第一交叉触发信号，并且响应于检测到第一交叉触发信号而执行动作。

5. 发明申请

US20120146658A1 DEBUG STATE MACHINE CROSS TRIGGERING 有权
标题翻译：调试状态机交叉触发
公开(公告)号：US20120146658A1
公开(公告)日：2012-06-14
申请号：US12980842
申请日：2010-12-29
申请人： Eric M. Rentschler , Steven J. Kommrusch , Elizabeth M. Cooper , Stephen Ennis
发明人： Eric M. Rentschler , Steven J. Kommrusch , Elizabeth M. Cooper , Stephen Ennis
IPC分类号： G01R31/02
CPC分类号： G06F11/3632 , G01R31/31705 , G06F11/3656
摘要： An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.
摘要翻译：电子系统的实施例包括第一电子模块，第二电子模块，与第一电子模块集成的第一调试电路，与第二电子模块集成的第二调试电路，以及第一调试电路和第二调试电路之间的通信接口第二调试电路。第一调试电路被配置为响应于确定触发事件已经发生而确定触发事件已经发生，并且在通信接口上产生第一交叉触发信号。第二调试电路被配置为检测通信接口上的第一交叉触发信号，并且响应于检测到第一交叉触发信号而执行动作。

6. 发明申请

US20120150474A1 DEBUG STATE MACHINE CROSS TRIGGERING 审中-公开
标题翻译：调试状态机交叉触发
公开(公告)号：US20120150474A1
公开(公告)日：2012-06-14
申请号：US12980849
申请日：2010-12-29
申请人： Eric M. Rentschler , Steven J. Kommrusch , Elizabeth M. Cooper , Stephen Ennis
发明人： Eric M. Rentschler , Steven J. Kommrusch , Elizabeth M. Cooper , Stephen Ennis
IPC分类号： G06F19/00
CPC分类号： G01R31/31705
摘要： In an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each of which is integrated with one of the plurality of electronic modules, a method for performing debug operations is performed by the plurality of debug circuits. The method includes each of the plurality of debug circuits producing a first cross trigger signal on a communications interface between the plurality of debug circuits, where the first cross trigger signal indicates that a triggering event has not occurred. The method further includes each of the plurality of debug circuits determining whether the triggering event has occurred, and in response to determining that the triggering event has occurred, each of the plurality of debug circuits producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.
摘要翻译：在包括多个电子模块和多个调试电路的电子系统中，每个调试电路与多个电子模块之一集成在一起，用于执行调试操作的方法由多个调试电路执行。该方法包括多个调试电路中的每一个在多个调试电路之间的通信接口上产生第一交叉触发信号，其中第一交叉触发信号指示未发生触发事件。该方法还包括多个调试电路中的每一个确定触发事件是否已经发生，并且响应于确定触发事件已经发生，多个调试电路中的每一个在通信接口上产生第二交叉触发信号，表示触发事件已发生。

7. 发明授权

US08180944B2 Guest interrupt manager that records interrupts for guests and delivers interrupts to executing guests 有权
标题翻译：客人中断管理器记录客人的中断，并传送执行客人的中断
公开(公告)号：US08180944B2
公开(公告)日：2012-05-15
申请号：US12611607
申请日：2009-11-03
申请人： Benjamin C. Serebrin , John F Wiederhirn , Elizabeth M. Cooper , Mark D. Hummel
发明人： Benjamin C. Serebrin , John F Wiederhirn , Elizabeth M. Cooper , Mark D. Hummel
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/45558 , G06F2009/45579
摘要： In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt manager is configured to record the interrupt in a data structure in the memory system to ensure that the interrupt is delivered to the guest even if the guest is not active in the system at a time that the interrupt message is received.
摘要翻译：在一个实施例中，系统包括存储器系统和来宾中断管理器。访客中断管理器被配置为接收与针对系统上的可访客可执行文件的中断相对应的中断消息。访客中断管理器被配置为在存储器系统中的数据结构中记录中断，以确保即使在接收到中断消息的时候客户机在系统中不活动，中断也被传递给客户机。

8. 发明申请

US20100191888A1 Guest Interrupt Manager to Aid Interrupt Virtualization 有权
标题翻译：客户中断管理器帮助中断虚拟化
公开(公告)号：US20100191888A1
公开(公告)日：2010-07-29
申请号：US12611607
申请日：2009-11-03
申请人： Benjamin C. Serebrin , John F. Wiederhirn , Elizabeth M. Cooper , Mark D. Hummel
发明人： Benjamin C. Serebrin , John F. Wiederhirn , Elizabeth M. Cooper , Mark D. Hummel
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/45558 , G06F2009/45579
摘要： In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt manager is configured to record the interrupt in a data structure in the memory system to ensure that the interrupt is delivered to the guest even if the guest is not active in the system at a time that the interrupt message is received.
摘要翻译：在一个实施例中，系统包括存储器系统和来宾中断管理器。访客中断管理器被配置为接收与针对系统上的可访客可执行文件的中断相对应的中断消息。访客中断管理器被配置为在存储器系统中的数据结构中记录中断，以确保即使在接收到中断消息的时候客户机在系统中不活动，中断也被传递给客户机。

9. 发明授权

US6047357A High speed method for maintaining cache coherency in a multi-level, set associative cache hierarchy 失效
标题翻译：用于在多级，组合关联高速缓存层级中维护高速缓存一致性的高速方法
公开(公告)号：US6047357A
公开(公告)日：2000-04-04
申请号：US379048
申请日：1995-01-27
申请人： Peter J. Bannon , Elizabeth M. Cooper
发明人： Peter J. Bannon , Elizabeth M. Cooper
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/0831 , G06F2212/601
摘要： A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.
摘要翻译：高速缓冲存储器系统包括以分层方式布置的多个高速缓存级别。存储在较高级别高速缓存级别的数据项目也存储在所有较低级别的高速缓存中。在较高级别的缓存的初始查找期间检测到最新版本的数据项。较高级别高速缓存的初始查找包括下一级较低级缓存的地址位的比较。因此，能够检测数据项的最新版本，而无需对下一级缓存进行附加查找。

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