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1. 发明授权

US08365114B2 Logic modification synthesis 有权
标题翻译：逻辑修改综合
公开(公告)号：US08365114B2
公开(公告)日：2013-01-29
申请号：US12862838
申请日：2010-08-25
申请人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
发明人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505
摘要： Two circuits, an original and a modified, are being recognized, with the original circuit having a first logic and the modified circuit having a second logic. The second logic contains at least one desired logic change relative to the first logic. An equivalence line is detected in the original circuit such that the first and second logic are equivalent from the circuit inputs to the equivalence line. At least one point of change is located amongst the logic gates that are neighboring the equivalence line. The points of change are accepted as verified if an observability condition is fulfilled. The observability condition is checked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verified points of change is derived using SAT and Boolean equation solving techniques, in such manner that the first logic becomes equivalent to the second logic.
摘要翻译：正在识别两个电路，一个原始和一个修改的电路，原始电路具有第一逻辑，并且该修改的电路具有第二逻辑。第二逻辑包含相对于第一逻辑的至少一个期望的逻辑变化。在原始电路中检测到等效线，使得第一和第二逻辑等效于从电路输入到等价线。至少一个变化点位于与等价线相邻的逻辑门之间。如果可观察性条件得到满足，则可以接受更改点。可观察性条件在布尔满足度（SAT）公式中进行检查。通过使用SAT和布尔方程求解技术，使得第一逻辑变为等同于第二逻辑的方式，导出用于验证的变化点的替代逻辑。

2. 发明申请

US20120054698A1 LOGIC MODIFICATION SYNTHESIS 有权
标题翻译：逻辑修改合成
公开(公告)号：US20120054698A1
公开(公告)日：2012-03-01
申请号：US12862838
申请日：2010-08-25
申请人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
发明人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer-executed method is disclosed which recognizes two circuits, an original and a modified circuit, with the original circuit having a first logic and the modified circuit having a second logic. The second logic is obtained by converting a modified specification into a preliminary gate-level form. The second logic contains at least one desired logic change relative to the first logic in order to realize the modified specification. The method includes detecting an equivalence line in the original circuit, such that the first and second logic are equivalent from the circuit inputs to the equivalence line, and finding at least one point of change amongst the logic gates that are neighboring the equivalence line. Next, accepting the points of change as verified point of change if an observability condition is fulfilled, which means that for every input vector for which an output of the original and modified circuits differ, at least one logic value of the points of change propagate to that output of the original circuit. This observability condition is checked within a Boolean Satisfiability (SAT) formulation. The method also includes deriving a substitute logic for the verified points of change, using SAT techniques, and Boolean equation solving techniques which solve for a change function at each point of change, in such manner that the first logic in the original circuit becomes equivalent to the second logic, and thereby implements the changed specification.
摘要翻译：公开了一种计算机执行方法，其识别具有第一逻辑的原始电路的两个电路，原始电路和修改的电路，并且修改的电路具有第二逻辑。通过将修改的规范转换成初级门级形式来获得第二逻辑。第二逻辑包含相对于第一逻辑的至少一个期望的逻辑变化，以便实现修改的规范。该方法包括检测原始电路中的等效线，使得第一和第二逻辑等效于从等效线路的电路输入，并找到与等价线相邻的逻辑门之间的至少一个变化点。接下来，如果满足可观察性条件，则将变化点接受为经验证的变化点，这意味着对于原始和修正电路的输出不同的每个输入向量，改变点的至少一个逻辑值传播到原始电路的输出。在布尔满足度（SAT）公式中检查此可观察性条件。该方法还包括使用SAT技术，以及在每个变化点解决变化函数的布尔方程求解技术，以使得原始电路中的第一逻辑等同于第二个逻辑，从而实现改变的规范。

3. 发明授权

US07373615B2 Method for optimization of logic circuits for routability 失效
标题翻译：用于优化可布线性逻辑电路的方法
公开(公告)号：US07373615B2
公开(公告)日：2008-05-13
申请号：US10780140
申请日：2004-02-17
申请人： William E. Dougherty, Jr. , Victor Kravets , Prabhakar N. Kudva , Andrew J. Sullivan
发明人： William E. Dougherty, Jr. , Victor Kravets , Prabhakar N. Kudva , Andrew J. Sullivan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design. Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.
摘要翻译：随着芯片复杂度的增加，VLSI芯片的可路由性（或布线拥塞）变得越来越重要。拥塞对性能，产量和芯片面积有重大影响。本发明在物理设计之前针对技术独立综合早期拥塞的优化。我们不是试图优化逻辑结构以及电路的空间布局，而是将这样的优化限制在逻辑综合的范围之内。也就是说，我们提出了一种积极的优化方法，在技术独立合成中识别电路结构，并产生更可预测的实现，从而提供更好的可路由性和产量。

4. 发明申请

US20050108674A1 Method, system and computer program product for implementing uncertainty in integrated circuit designs with programmable logic 失效
标题翻译：用于实现具有可编程逻辑的集成电路设计中的不确定性的方法，系统和计算机程序产品
公开(公告)号：US20050108674A1
公开(公告)日：2005-05-19
申请号：US10714750
申请日：2003-11-17
申请人： John Darringer , George Doerre , Victor Kravets
发明人： John Darringer , George Doerre , Victor Kravets
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints. Generating involves using integrated circuit specification language extensions that include an Uncertain Function that is used in place of a logic function or operator, an Uncertain Function Assertion for imposing at least one constraint on the Uncertain Function, an Uncertain. Register for a register having a programmable size within a specified range and an Uncertain Constant.
摘要翻译：公开了一种用于指定集成电路的方法，系统和计算机程序产品。集成电路包括硬连线专用逻辑技术部分和可编程特定逻辑技术部分。该方法包括通过将每个不确定逻辑函数映射到其抽象可编程逻辑元件实现并通过将每个已知逻辑功能映射到与技术无关的逻辑元件实现来生成混合逻辑网络; 使用逻辑综合优化简化混合逻辑网络; 通过将抽象可编程逻辑元件实现映射到特定可编程逻辑技术和与技术无关的逻辑元件实现到特定逻辑技术，将简化的混合逻辑网络映射到特定技术; 并且还包括优化映射网络以满足性能约束。生成涉及使用集成电路规范语言扩展，包括用于代替逻辑功能或运算符的不确定函数，用于对不确定函数施加至少一个约束的不确定函数断言。注册具有规定范围内可编程大小的寄存器和不确定常数。

5. 发明申请

US20080195984A1 METHOD FOR OPTIMIZATION OF LOGIC CIRCUITS FOR ROUTABILITY IMPROVEMENT 审中-公开
标题翻译：优化逻辑电路的方法，用于不可改善的改进
公开(公告)号：US20080195984A1
公开(公告)日：2008-08-14
申请号：US12104852
申请日：2008-04-17
申请人： William E. Dougherty, , Victor Kravets , Prabhakar N. Kudva , Andrew J. Sullivan
发明人： William E. Dougherty, , Victor Kravets , Prabhakar N. Kudva , Andrew J. Sullivan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design.Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.
摘要翻译：随着芯片复杂度的增加，VLSI芯片的可路由性（或布线拥塞）变得越来越重要。拥塞对性能，产量和芯片面积有重大影响。本发明在物理设计之前针对技术独立综合早期拥塞的优化。我们不是试图优化逻辑结构以及电路的空间布局，而是将这样的优化限制在逻辑综合的范围之内。也就是说，我们提出了一种积极的优化方法，在技术独立合成中识别电路结构，并产生更可预测的实现，从而提供更好的可路由性和产量。

6. 发明申请

US20070050746A1 Method and System Product for Implementing Uncertainty in Integrated Circuit Designs with Programmable Logic 失效
标题翻译：用可编程逻辑实现集成电路设计中的不确定性的方法和系统产品
公开(公告)号：US20070050746A1
公开(公告)日：2007-03-01
申请号：US11553076
申请日：2006-10-26
申请人： John Darringer , George Doerre , Victor Kravets
发明人： John Darringer , George Doerre , Victor Kravets
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints. Generating involves using integrated circuit specification language extensions that include an Uncertain Function that is used in place of a logic function or operator, an Uncertain Function Assertion for imposing at least one constraint on the Uncertain Function, an Uncertain Register for a register having a programmable size within a specified range and an Uncertain Constant.
摘要翻译：公开了一种用于指定集成电路的方法，系统和计算机程序产品。集成电路包括硬连线专用逻辑技术部分和可编程特定逻辑技术部分。该方法包括通过将每个不确定逻辑函数映射到其抽象可编程逻辑元件实现并通过将每个已知逻辑功能映射到与技术无关的逻辑元件实现来生成混合逻辑网络; 使用逻辑综合优化简化混合逻辑网络; 通过将抽象可编程逻辑元件实现映射到特定可编程逻辑技术和与技术无关的逻辑元件实现到特定逻辑技术，将简化的混合逻辑网络映射到特定技术; 并且还包括优化映射网络以满足性能约束。生成涉及使用集成电路规范语言扩展，包括用于代替逻辑功能或运算符的不确定函数，用于对不确定函数施加至少一个约束的不确定函数断言，具有可编程大小的寄存器的不确定寄存器在指定范围内和不确定常数。

7. 发明申请

US20050183046A1 Method for optimization of logic circuits for routability 失效
标题翻译：用于优化可布线性逻辑电路的方法
公开(公告)号：US20050183046A1
公开(公告)日：2005-08-18
申请号：US10780140
申请日：2004-02-17
申请人： William Dougherty , Victor Kravets , Prabhakar Kudva , Andrew Sullivan
发明人： William Dougherty , Victor Kravets , Prabhakar Kudva , Andrew Sullivan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design. Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.
摘要翻译：随着芯片复杂度的增加，VLSI芯片的可路由性（或布线拥塞）变得越来越重要。拥塞对性能，产量和芯片面积有重大影响。本发明在物理设计之前针对技术独立综合早期拥塞的优化。我们不是试图优化逻辑结构以及电路的空间布局，而是将这样的优化限制在逻辑综合的范围之内。也就是说，我们提出了一种积极的优化方法，在技术独立合成中识别电路结构，并产生更可预测的实现，从而提供更好的可路由性和产量。

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