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    • 7. 发明授权
    • Transferring data between cache memory and a media access controller
    • 在缓存和介质访问控制器之间传输数据
    • US06920529B2
    • 2005-07-19
    • US10105857
    • 2002-03-25
    • Fred GrunerRobert HathawayRicardo Ramirez
    • Fred GrunerRobert HathawayRicardo Ramirez
    • G06F12/00G06F12/08H04L12/56G06F13/00
    • H04L47/10G06F12/0813G06F12/0831G06F12/084H04L47/12H04L47/20H04L47/2441H04L47/765H04L47/805H04L47/822
    • A coprocessor transfers data between media access controllers and a set of cache memory without accessing main memory. The coprocessor includes a reception media access controller that receives data from a network and a transmission media access controller that transmits data to a network. A streaming output data transfer engine in the coprocessor transfers data from the reception media access controller to cache memory. A streaming input data transfer engine in the coprocessor transfers data from cache memory to the transmission media access controller. The coprocessor's data transfer engines transfer data between cache memory and the media access controllers in a single data transfer operation—eliminating the need to store data in an intermediary memory location between the cache memory and data transfer engines. In one implementation, the coprocessor is employed in a compute engine that performs different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.
    • 协处理器在介质访问控制器和一组高速缓冲存储器之间传输数据,而不访问主存储器。 协处理器包括从网络接收数据的接收媒体接入控制器和向网络发送数据的传输媒体接入控制器。 协处理器中的流输出数据传输引擎将数据从接收媒体访问控制器传送到高速缓冲存储器。 协处理器中的流式输入数据传输引擎将数据从高速缓冲存储器传送到传输介质访问控制器。 协处理器的数据传输引擎在单个数据传输操作中在高速缓冲存储器和媒体访问控制器之间传输数据,从而无需将数据存储在高速缓冲存储器和数据传输引擎之间的中间存储器位置。 在一个实现中,协处理器被用在执行不同网络服务的计算引擎中,包括但不限于:1)虚拟专用网; 2)安全套接字层处理; 3)网页缓存; 4)超文本标记语言压缩; 5)病毒检查; 6)防火墙支持; 和7)网页切换。
    • 8. 发明授权
    • Compute engine employing a coprocessor
    • 采用协处理器的计算引擎
    • US06901488B2
    • 2005-05-31
    • US10105587
    • 2002-03-25
    • Fred GrunerRobert HathawayRicardo Ramirez
    • Fred GrunerRobert HathawayRicardo Ramirez
    • G06F12/00G06F12/08H04L12/56G06F13/00
    • H04L47/10G06F12/0813G06F12/0831G06F12/084H04L47/12H04L47/20H04L47/2441H04L47/765H04L47/805H04L47/822
    • A compute engine includes a central processing unit coupled to a coprocessor. The coprocessor includes a sequencer coupled to a set of application engines for performing operations assigned to the compute engine. The sequencer is coupled to application engines through a set of data, enable, and control interfaces. An arbiter couples the sequencer and application engines to memory. Alternatively, the coprocessor may include multiple sequencers, with each sequencer being coupled to a different set of application engines. One set of application engines includes a media access controller for communicating with a network and a data transfer engine coupling the media access controller to the arbiter. In one implementation, application engines facilitate different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.
    • 计算引擎包括耦合到协处理器的中央处理单元。 协处理器包括耦合到一组应用引擎的定序器,用于执行分配给计算引擎的操作。 定序器通过一组数据,启用和控制接口耦合到应用程序引擎。 仲裁者将定序器和应用引擎耦合到内存中。 或者,协处理器可以包括多个定序器,每个定序器耦合到不同的应用引擎集合。 一组应用引擎包括用于与网络通信的媒体访问控制器和将媒体访问控制器耦合到仲裁器的数据传输引擎。 在一个实现中,应用引擎促进不同的网络服务,包括但不限于:1)虚拟专用网; 2)安全套接字层处理; 3)网页缓存; 4)超文本标记语言压缩; 5)病毒检查; 6)防火墙支持; 和7)网页切换。
    • 9. 发明授权
    • Streaming output engine facilitating data transfers between application engines and memory
    • 流输出引擎促进应用引擎和内存之间的数据传输
    • US06754774B2
    • 2004-06-22
    • US10105497
    • 2002-03-25
    • Fred GrunerRicardo Ramirez
    • Fred GrunerRicardo Ramirez
    • G06F1200
    • H04L47/10G06F12/0813G06F12/0831G06F12/084H04L47/12H04L47/20H04L47/2441H04L47/765H04L47/805H04L47/822
    • A system includes a memory, a sequencer, and a set of application engines in communication with the sequencer and memory. The set of application engines includes a streaming output engine with a storage engine, alignment circuit, and data buffer. The storage engine includes a memory opcode output and memory address output in communication with the memory. The storage engine employs these outputs to access the memory by supplying memory transaction opcodes and memory addresses. The alignment circuit receives data from other application engines in the set of application engines. In operation, the alignment circuit aligns data transfers from an application engine into a data word. The data buffer stores data words from the alignment circuit and transfers them to locations accessed in the memory by the storage engine.
    • 系统包括与定序器和存储器通信的存储器,定序器和一组应用引擎。 该套应用引擎包括具有存储引擎,对准电路和数据缓冲器的流输出引擎。 存储引擎包括与存储器通信的存储器操作码输出和存储器地址输出。 存储引擎使用这些输出来通过提供存储器事务操作码和存储器地址来访问存储器。 对准电路从应用引擎集合中的其他应用引擎接收数据。 在操作中,对准电路将来自应用引擎的数据传输对准数据字。 数据缓冲器存储来自对准电路的数据字,并将它们传送到存储引擎在存储器中访问的位置。