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1. 发明授权

US06525350B1 Semiconductor integrated circuit basic cell semiconductor integrated circuit using the same 有权
标题翻译：半导体集成电路基本单元半导体集成电路采用相同的方式
公开(公告)号：US06525350B1
公开(公告)日：2003-02-25
申请号：US09613769
申请日：2000-07-11
申请人： Eita Kinoshita , Makoto Mizuno
发明人： Eita Kinoshita , Makoto Mizuno
IPC分类号： H01L2710
CPC分类号： H01L27/118 , H01L27/0207
摘要： A basic cell is disclosed, which is small in area and has sufficient connection flexibility. for achieving a semiconductor integrated circuit with a higher density and a reduced manufacturing cost. In a basic cell, a terminal wire, which is connected to a transistor terminal with a contact, is placed in a first metal wiring layer, and a plurality of terminal wire connection points, which can be connected to a second metal wire through a first via, are provided on the terminal wire. Further, in a semiconductor integrated circuit, a circuit wire in a second metal wiring layer is placed along grid points with a fixed pitch, and is connected to a terminal connection point of a transistor terminal, which is displaced from the grid points, through a terminal wire provided in the first metal wiring layer.
摘要翻译：公开了一种面积小且具有足够的连接灵活性的基本单元。用于实现具有更高密度和降低制造成本的半导体集成电路。在基本单元中，连接到具有触点的晶体管端子的端子线被放置在第一金属布线层中，并且多个端子线连接点可以通过第一金属线连接到第二金属线通孔，设置在端子线上。此外，在半导体集成电路中，第二金属布线层中的电路布线沿着网格点以固定的间距放置，并且连接到从网格点移位的晶体管端子的端子连接点端子线设置在第一金属布线层中。

2. 发明授权

US07432115B2 Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit 有权
标题翻译：测试电路，具有测试电路的半导体产品晶片，以及使用测试电路监测制造工艺的方法
公开(公告)号：US07432115B2
公开(公告)日：2008-10-07
申请号：US11808861
申请日：2007-06-13
申请人： Eita Kinoshita
发明人： Eita Kinoshita
IPC分类号： H01L21/00
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.
摘要翻译：提供了使用该测试电路监测半导体集成电路的制造工艺的测试电路和方法。测试电路包括要测试的元件; 选择电路，用于一次顺序地选择所述元件中的至少一个。用于测试元件的测试电路和焊盘被放置在半导体晶片上的划线内。

3. 发明授权

US5373178A MOSFET with sidewall spacer on gate section 失效
标题翻译：栅极侧壁间隔MOSFET
公开(公告)号：US5373178A
公开(公告)日：1994-12-13
申请号：US095540
申请日：1993-07-26
申请人： Makoto Motoyoshi , Eita Kinoshita
发明人： Makoto Motoyoshi , Eita Kinoshita
IPC分类号： H01L27/11 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/76801 , H01L21/823864 , H01L21/823871 , H01L29/7833 , Y10S257/90
摘要： After forming a low concentration impurity layer by ion implanting an impurity into a semiconductor substrate 1 by using a gate electrode 7 on the semiconductor substrate 1 as a mask, side walls composed of films having a large etching resistivity with respect to an interlayer dielectric film 13 are formed on side surfaces of the gate electrode 7 and a gate oxide film 6 located beneath the gate electrode 7. Subsequently, the interlayer dielectric film 13 is formed over the whole surface, and a contact hole 18 having a part of side walls constituted by the first-mentioned side walls 8 and a field oxide film 2 is formed. A high concentration impurity layer is formed by implanting an impurity through the contact hole 18.
摘要翻译：通过使用半导体衬底1上的栅电极7作为掩模将杂质离子注入半导体衬底1中形成低浓度杂质层之后，由相对于层间绝缘膜13具有大的蚀刻电阻率的膜构成的侧壁形成在栅电极7的侧面和位于栅电极7下方的栅极氧化膜6.接着，在整个表面上形成层间电介质膜13，并且具有由侧壁构成的侧壁的一部分的接触孔18 首先形成侧壁8和场氧化膜2。通过将杂质注入接触孔18而形成高浓度杂质层。

4. 发明申请

US20050090922A1 Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit 审中-公开
标题翻译：测试电路，具有测试电路的半导体产品晶片，以及使用测试电路监测制造工艺的方法
公开(公告)号：US20050090922A1
公开(公告)日：2005-04-28
申请号：US10989355
申请日：2004-11-17
申请人： Eita Kinoshita
发明人： Eita Kinoshita
IPC分类号： H01L23/544 , H01L21/66 , G01R31/26 , G06F19/00 , H01L23/58 , H01L29/10
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.
摘要翻译：提供了使用该测试电路监测半导体集成电路的制造工艺的测试电路和方法。测试电路包括要测试的元件; 选择电路，用于一次顺序地选择所述元件中的至少一个。用于测试元件的测试电路和焊盘被放置在半导体晶片上的划线内。

5. 发明授权

US06204542B1 Field effect transistor with improved driving capability 有权
标题翻译：具有改善驱动能力的场效应晶体管
公开(公告)号：US06204542B1
公开(公告)日：2001-03-20
申请号：US09161916
申请日：1998-09-29
申请人： Eita Kinoshita , Yoshitaka Kimura , Shigeo Iida
发明人： Eita Kinoshita , Yoshitaka Kimura , Shigeo Iida
IPC分类号： H01L2710
CPC分类号： H01L29/41725 , H01L27/0207 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： The gate width of a field effect transistor is increased to a value greater than a size of an active region by forming an inclined portion of a gate electrode. As a result, the current driving capability of a field effect transistor is increased without degrading the integration density. The driving capability of the transistor can be further effectively increased by forming an expanded portion of the active region at a location corresponding to the inclined portion of the gate electrode thereby reducing the resistance of the diffusion layer.
摘要翻译：通过形成栅电极的倾斜部分，将场效应晶体管的栅极宽度增加到大于有源区的尺寸的值。结果，增加了场效应晶体管的电流驱动能力，而不降低集成密度。通过在对应于栅电极的倾斜部分的位置处形成有源区的扩展部分，从而降低扩散层的电阻，能够进一步有效地提高晶体管的驱动能力。

6. 发明申请

US20070244593A1 Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit 有权
标题翻译：测试电路，具有测试电路的半导体产品晶片，以及使用测试电路监测制造工艺的方法
公开(公告)号：US20070244593A1
公开(公告)日：2007-10-18
申请号：US11808861
申请日：2007-06-13
申请人： Eita Kinoshita
发明人： Eita Kinoshita
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.
摘要翻译：提供了使用该测试电路监测半导体集成电路的制造工艺的测试电路和方法。测试电路包括要测试的元件; 选择电路，用于一次顺序地选择所述元件中的至少一个。用于测试元件的测试电路和焊盘被放置在半导体晶片上的划线内。

7. 发明授权

US06836133B2 Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit 有权
标题翻译：测试电路，具有测试电路的半导体产品晶片，以及使用测试电路监测制造工艺的方法
公开(公告)号：US06836133B2
公开(公告)日：2004-12-28
申请号：US10115972
申请日：2002-04-05
申请人： Eita Kinoshita
发明人： Eita Kinoshita
IPC分类号： G01R3126
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.
摘要翻译：提供了使用该测试电路监测半导体集成电路的制造工艺的测试电路和方法。测试电路包括要测试的元件; 选择电路，用于一次顺序地选择所述元件中的至少一个。用于测试元件的测试电路和焊盘被放置在半导体晶片上的划线内。

8. 发明授权

US4950376A Method of gas reaction process control 失效
标题翻译：气体反应过程控制方法
公开(公告)号：US4950376A
公开(公告)日：1990-08-21
申请号：US317201
申请日：1989-02-28
申请人： Yutaka Hayashi , Yasushi Kondo , Kenichi Ishii , Eita Kinoshita
发明人： Yutaka Hayashi , Yasushi Kondo , Kenichi Ishii , Eita Kinoshita
IPC分类号： C23F4/00 , C23C16/511 , H01J37/32 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31
CPC分类号： H01J37/32623 , C23C16/511 , H01J37/3299 , H01J2237/004
摘要： A method of gas reaction process control in which plasma gas generated in a location different than a location at which a specimen is held is transported to a location at which the specimen is held and gas processing of the specimen is carried out. A control electrode with porous structure permeable to the plasma gas is provided in the transportation route and a voltage is applied to the control electrode voltage for adjusting the specimen surface potential so as to prevent degradation of the specimen due to specimen surface potential.
摘要翻译：一种气体反应过程控制方法，其中在与保持试样的位置不同的位置产生的等离子体气体被输送到保持试样的位置，并且进行样品的气体处理。在输送路径中设置具有可渗透等离子体气体的多孔结构的控制电极，对控制电极电压施加电压，调整试样表面电位，以防止样品表面电位劣化。

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