专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6020238A Method of fabricating a high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory 失效
标题翻译：制造用于低电压非易失性存储器的高介电常数多晶硅介电结构的方法
公开(公告)号：US6020238A
公开(公告)日：2000-02-01
申请号：US978107
申请日：1997-11-25
申请人： Yue-Song He , Effiong Ibok
发明人： Yue-Song He , Effiong Ibok
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method of fabricating an interpolysilicon dielectric structure in a non-volatile memory includes the steps of forming a nitride layer 12 on a floating gate 10 and a high dielectric constant layer 14 on the nitride layer 12. A control gate 18 may be formed directly on the high dielectric constant layer 14, or on a thin layer 16 of an oxide or an oxynitride on the high dielectric constant layer 14.
摘要翻译：在非易失性存储器中制造多晶硅介质结构的方法包括在氮化物层12上的浮置栅极10和高介电常数层14上形成氮化物层12的步骤。控制栅极18可直接形成在高介电常数层14或在高介电常数层14上的氧化物或氧氮化物的薄层16上。

2. 发明授权

US5940718A Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation 失效
标题翻译：在自对准浅沟槽隔离中，氮化辅助多晶硅侧壁保护
公开(公告)号：US5940718A
公开(公告)日：1999-08-17
申请号：US119715
申请日：1998-07-20
申请人： Effiong Ibok , Yue-Song He , Yowjuang W. Liu
发明人： Effiong Ibok , Yue-Song He , Yowjuang W. Liu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： A method for fabricating a semiconductor device including a silicon substrate and plural silicon stacks thereon includes forming a nitride shield layer on the substrate and stacks to cover the stacks, such that the stacks are protected from loss of critical dimension during subsequent isolation trench formation and oxidation. In other words, the edge of each stack, and thus the critical dimension of the silicon layers of the stack, is protected from oxidation by the nitride shield layer.
摘要翻译：一种用于制造包括硅衬底和其上的多个硅堆叠的半导体器件的方法包括在衬底上形成氮化物屏蔽层并堆叠以覆盖堆叠，使得在随后的隔离沟槽形成和氧化期间保护堆叠免受临界尺寸的损失。换句话说，每个堆叠的边缘以及因此堆叠的硅层的临界尺寸被氮化物屏蔽层防止氧化。

3. 发明授权

US6025228A Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory 失效
标题翻译：制造用于低电压非易失性存储器的氮氧化物封端的高介电常数多晶硅介电结构的方法
公开(公告)号：US6025228A
公开(公告)日：2000-02-15
申请号：US978398
申请日：1997-11-25
申请人： Effiong Ibok , Yue-Song He
发明人： Effiong Ibok , Yue-Song He
IPC分类号： H01L21/28 , H01L21/70
CPC分类号： H01L21/28273
摘要： A method of fabricating an interpolysilicon dielectric structure in a non-volatile memory includes the steps of forming a high dielectric constant layer 12 on a floating gate 10 and an oxynitride layer 14 on the high dielectric constant layer 12. A control gate 18 may be formed on the oxynitride layer 14 to produce a dual gate structure with a high capacitance and therefore a high coupling ratio.
摘要翻译：在非易失性存储器中制造多晶硅介质结构的方法包括在高介电常数层12上的浮置栅极10和氧氮化物层14上形成高介电常数层12的步骤。可以形成控制栅极18 在氮氧化物层14上产生具有高电容并因此具有高耦合比的双栅极结构。

4. 发明授权

US07816726B2 Nonvolatile memories with laterally recessed charge-trapping dielectric 有权
标题翻译：具有横向凹陷的电荷俘获电介质的非易失性存储器
公开(公告)号：US07816726B2
公开(公告)日：2010-10-19
申请号：US11961183
申请日：2007-12-20
申请人： Yue-Song He , Len Mei
发明人： Yue-Song He , Len Mei
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42344
摘要： Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.
摘要翻译：非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

5. 发明申请

US20090184359A1 Split-gate non-volatile memory devices having nitride tunneling layers 审中-公开
标题翻译：具有氮化物隧穿层的分离栅非易失性存储器件
公开(公告)号：US20090184359A1
公开(公告)日：2009-07-23
申请号：US12017961
申请日：2008-01-22
申请人： Yue-Song He , Len Mei
发明人： Yue-Song He , Len Mei
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/42344
摘要： A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate.
摘要翻译：具有与单元堆叠相邻形成的单元堆叠和选择栅极的存储器件。电池堆包括形成在衬底的沟道区上的第一无陷波氮化物层，形成在第一氮化物层上的第二氮化物层，形成在第二氮化物层上的氧化物层， K氧化物层和作为选择栅极的多隔板作为与控制栅极相邻形成。

6. 发明授权

US07079424B1 Methods and systems for reducing erase times in flash memory devices 有权
标题翻译：用于减少闪存设备中擦除时间的方法和系统
公开(公告)号：US07079424B1
公开(公告)日：2006-07-18
申请号：US10945914
申请日：2004-09-22
申请人： Sungchul Lee , Sheunghee Park , Yue-Song He , Ming Sang Kwan
发明人： Sungchul Lee , Sheunghee Park , Yue-Song He , Ming Sang Kwan
IPC分类号： G11C11/34
CPC分类号： G11C16/107 , G11C16/16 , G11C16/3468
摘要： A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level. The memory cell may be erased to lower the threshold voltage of the memory cell to a second predetermined level.
摘要翻译：提供一种用于擦除具有衬底，控制栅极，浮置栅极，源极区域和漏极区域的存储器单元的方法。该方法包括对存储器单元预编程以将存储器单元的阈值电压升高到第一预定电平，其中预编程存储器单元不包括用于确保存储器单元的阈值电压已被提高的验证过程到第一预定水平。可以擦除存储器单元以将存储器单元的阈值电压降低到第二预定电平。

7. 发明授权

US06898124B1 Efficient and accurate sensing circuit and technique for low voltage flash memory devices 有权
标题翻译：高效，准确的低压闪存器件感测电路和技术
公开(公告)号：US06898124B1
公开(公告)日：2005-05-24
申请号：US10678446
申请日：2003-10-03
申请人： Zhigang Wang , Nian Yang , Yue-Song He
发明人： Zhigang Wang , Nian Yang , Yue-Song He
IPC分类号： G11C11/56 , G11C16/06 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642
摘要： An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.
摘要翻译：示例性感测电路包括连接到第一节点的第一晶体管，其中目标存储器单元具有能够在涉及目标存储器单元的读取操作期间通过选择电路连接到第一节点的漏极。感测电路还包括连接到第一晶体管的去耦电路。解耦电路包括具有耦合到第一晶体管的栅极的栅极的第二晶体管。去耦电路还具有大于1的去耦系数（N）。第二晶体管的漏极通过偏置电阻器在第二节点连接到参考电压。利用该布置，第二晶体管的漏极在第二节点处产生感测放大器输入电压，使得感测放大器输入电压与第一节点分离。

8. 发明授权

US06833297B1 Method for reducing drain induced barrier lowering in a memory device 有权
标题翻译：用于减少存储器件中的漏极引起的屏障降低的方法
公开(公告)号：US06833297B1
公开(公告)日：2004-12-21
申请号：US10265001
申请日：2002-10-04
申请人： Richard M. Fastow , Yue-Song He , Nga-Ching Wong
发明人： Richard M. Fastow , Yue-Song He , Nga-Ching Wong
IPC分类号： H01L218234
CPC分类号： H01L29/66825 , H01L29/7883
摘要： The present invention is a method for fabricating a memory device. In one embodiment, a first impurity concentration is deposited in a channel region of a memory device. A second impurity concentration, which overlies the first impurity concentration, is then created in the channel region. Finally, a memory array is fabricated upon the channel region. The memory array overlies the first impurity concentration and the second impurity concentration.
摘要翻译：本发明是一种用于制造存储器件的方法。在一个实施例中，第一杂质浓度沉积在存储器件的沟道区中。然后在通道区域中产生第二杂质浓度，其覆盖第一杂质浓度。最后，在通道区域上制造存储器阵列。存储器阵列覆盖第一杂质浓度和第二杂质浓度。

9. 发明授权

US06177316B1 Post barrier metal contact implantation to minimize out diffusion for NAND device 有权
标题翻译：后阻挡金属接触植入，以最小化NAND器件的扩散
公开(公告)号：US06177316B1
公开(公告)日：2001-01-23
申请号：US09412278
申请日：1999-10-05
申请人： Yue-Song He , Kent K. Chang , John J. Wang
发明人： Yue-Song He , Kent K. Chang , John J. Wang
IPC分类号： H01L21336
CPC分类号： H01L21/28273
摘要： An improved method for fabricating a NAND-type memory cell structure. The present invention forgoes providing a contact mask implantation process prior to deposition of a metal barrier layer, which is a typical order of processing the NAND-type memory cell. Instead, in the present invention, the metal barrier layer is deposited on a core area of the NAND-type memory cell prior to contact mask implantation. Thereafter, the contact mask implantation process is performed on the structure in a conventional manner.
摘要翻译：一种用于制造NAND型存储单元结构的改进方法。本发明放弃在沉积金属阻挡层之前提供接触掩模注入工艺，这是处理NAND型存储单元的典型顺序。相反，在本发明中，在接触掩模植入之前，将金属阻挡层沉积在NAND型存储单元的核心区域上。此后，以常规方式对结构进行接触掩模注入工艺。

10. 发明授权

US6143608A Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation 有权
标题翻译：阻挡层在隧道氧化物氮化期间减少外围栅极区域的氮污染
公开(公告)号：US6143608A
公开(公告)日：2000-11-07
申请号：US283308
申请日：1999-03-31
申请人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
发明人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.
摘要翻译：本发明描述了在半导体芯片的周边区域中制造栅极氧化物区域的方法，其中栅极氧化物区域具有改善的电性能。所述方法包括在半导体芯片的周边上沉积阻挡层，以防止在半导体芯片的芯区域中的氮化步骤期间将杂质氮原子引入周围。通过防止周围的栅极区域的污染，如此产生的栅极氧化物区域具有增加的击穿电压和增加的可靠性。本发明描述了用于蚀刻用于保护周边免受隧道氧化物氮化的阻挡层的方法。用本发明的方法制造的半导体器件具有更长的预期寿命，并且可以以较高的器件密度制造。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式