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1. 再颁专利

USRE44551E1 Universal tuner for mobile TV 有权
标题翻译：通用调谐器用于手机电视
公开(公告)号：USRE44551E1
公开(公告)日：2013-10-22
申请号：US13645471
申请日：2012-10-04
申请人： Mohy Abdelgany , Frank Carr , Hassan Elwan , Amr Fahim , Edward Youssoufian
发明人： Mohy Abdelgany , Frank Carr , Hassan Elwan , Amr Fahim , Edward Youssoufian
IPC分类号： H04N5/50
CPC分类号： H04N5/50 , H03D3/007 , H03J1/005 , H04N21/41407
摘要： A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.
摘要翻译：用于移动电视设备的调谐器包括至少一个RF前端组件，其包括适于放大移动电视信号的LNA; 用于产生信号的PLL电路; 和一对混频器，用于接收来自LNA和PLL电路的信号，并对信号进行下变频; 连接到所述RF前端组件的模拟基带组件，其中所述模拟基带组件包括每个包括可调谐高阶阻抗滤波器的I和Q信道信号路径; 至少一个信号放大级; 以及信号滤波器级，其连接到所述信号放大级，其中所述模拟基带分量还包括可操作地连接到所述I和Q通道信号路径的多个开关，并且其中所述多个开关按照多个配置选择性地打开和关闭以允许调谐器接收所有移动电视标准的移动电视信号。

2. 发明申请

US20080259219A1 UNIVERSAL TUNER FOR MOBILE TV 有权
标题翻译：通用电视移动电视
公开(公告)号：US20080259219A1
公开(公告)日：2008-10-23
申请号：US11737222
申请日：2007-04-19
申请人： Mohy Abdelgany , Frank Carr , Hassan Elwan , Amr Fahim , Edward Youssoufian
发明人： Mohy Abdelgany , Frank Carr , Hassan Elwan , Amr Fahim , Edward Youssoufian
IPC分类号： H04N5/50
CPC分类号： H04N5/50 , H03D3/007 , H03J1/005 , H04N21/41407
摘要： A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.
摘要翻译：用于移动电视设备的调谐器包括至少一个RF前端组件，其包括适于放大移动电视信号的LNA; 用于产生信号的PLL电路; 和一对混频器，用于接收来自LNA和PLL电路的信号，并对信号进行下变频; 连接到所述RF前端组件的模拟基带组件，其中所述模拟基带组件包括每个包括可调谐高阶阻抗滤波器的I和Q信道信号路径; 至少一个信号放大级; 以及信号滤波器级，其连接到所述信号放大级，其中所述模拟基带分量还包括可操作地连接到所述I和Q通道信号路径的多个开关，并且其中所述多个开关按照多个配置选择性地打开和关闭以允许调谐器接收所有移动电视标准的移动电视信号。

3. 发明授权

US08005449B2 Subsampling wideband RSSI circuit 有权
标题翻译：二次采样宽带RSSI电路
公开(公告)号：US08005449B2
公开(公告)日：2011-08-23
申请号：US12136864
申请日：2008-06-11
申请人： Edward Youssoufian , Amr Fahim
发明人： Edward Youssoufian , Amr Fahim
IPC分类号： H04B17/00
CPC分类号： H04B1/1027 , H04B17/318
摘要： A Received Signal Strength Indicator (RSSI) circuit includes a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth; an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal; and a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The subsampling circuit and the ADC may operate as a single subsampling ADC. The RSSI circuit may further comprise ignoring higher order aliases at a multiple of the sampling frequency if the baseband detector is clocked at the sampling frequency.
摘要翻译：接收信号强度指示器（RSSI）电路包括子采样电路，其处理包括采样频率fs的输入信号，其中所述子采样电路对所述输入信号进行子采样，其中所述输入信号被二次采样以集中在窄带宽中的功率; 模数转换器（ADC），其可操作地连接到所述子采样电路，其中所述ADC对所述子采样信号进行数字化; 以及可操作地连接到ADC的基带检测器，其中基带检测器检测来自数字化的二次采样信号的功率并产生输出信号。子采样电路和ADC可以作为单个子采样ADC工作。如果基带检测器以采样频率计时，则RSSI电路还可以包括以采样频率的倍数忽略较高阶别名。

4. 发明授权

US07973861B2 Universal tuner for mobile TV 有权
标题翻译：通用调谐器用于手机电视
公开(公告)号：US07973861B2
公开(公告)日：2011-07-05
申请号：US11737222
申请日：2007-04-19
申请人： Mohy Abdelgany , Frank Carr , Hassan Elwan , Amr Fahim , Edward Youssoufian
发明人： Mohy Abdelgany , Frank Carr , Hassan Elwan , Amr Fahim , Edward Youssoufian
IPC分类号： H04N5/50
CPC分类号： H04N5/50 , H03D3/007 , H03J1/005 , H04N21/41407
摘要： A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.
摘要翻译：用于移动电视设备的调谐器包括至少一个RF前端组件，其包括适于放大移动电视信号的LNA; 用于产生信号的PLL电路; 和一对混频器，用于接收来自LNA和PLL电路的信号，并对信号进行下变频; 连接到所述RF前端组件的模拟基带组件，其中所述模拟基带组件包括每个包括可调谐高阶阻抗滤波器的I和Q信道信号路径; 至少一个信号放大级; 以及信号滤波器级，其连接到所述信号放大级，其中所述模拟基带分量还包括可操作地连接到所述I和Q通道信号路径的多个开关，并且其中所述多个开关按照多个配置选择性地打开和关闭以允许调谐器接收所有移动电视标准的移动电视信号。

5. 发明申请

US20090311985A1 SUBSAMPLING WIDEBAND RSSI CIRCUIT 有权
标题翻译： SUBSAMPLING宽带RSSI电路
公开(公告)号：US20090311985A1
公开(公告)日：2009-12-17
申请号：US12136864
申请日：2008-06-11
申请人： Edward Youssoufian , Amr Fahim
发明人： Edward Youssoufian , Amr Fahim
IPC分类号： H04B17/00
CPC分类号： H04B1/1027 , H04B17/318
摘要： A Received Signal Strength Indicator (RSSI) circuit includes a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth; an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal; and a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The subsampling circuit and the ADC may operate as a single subsampling ADC. The RSSI circuit may further comprise ignoring higher order aliases at a multiple of the sampling frequency if the baseband detector is clocked at the sampling frequency.
摘要翻译：接收信号强度指示器（RSSI）电路包括子采样电路，其处理包括采样频率fs的输入信号，其中所述子采样电路对所述输入信号进行子采样，其中所述输入信号被二次采样以集中在窄带宽中的功率; 模数转换器（ADC），可操作地连接到所述子采样电路，其中所述ADC对所述子采样信号进行数字化; 以及可操作地连接到ADC的基带检测器，其中基带检测器检测来自数字化的二次采样信号的功率并产生输出信号。子采样电路和ADC可以作为单个子采样ADC工作。如果基带检测器以采样频率计时，则RSSI电路还可以包括以采样频率的倍数忽略较高阶别名。

6. 发明授权

US07352238B2 dB-linear analog variable gain amplifier (VGA) realization system and method 有权
标题翻译： dB线性模拟可变增益放大器（VGA）实现系统和方法
公开(公告)号：US07352238B2
公开(公告)日：2008-04-01
申请号：US11472138
申请日：2006-06-21
申请人： Hassan Elwan , Amr Fahim , Aly Ismail , Edward Youssoufian
发明人： Hassan Elwan , Amr Fahim , Aly Ismail , Edward Youssoufian
IPC分类号： H03F1/36
CPC分类号： H03G7/06 , H03G1/0088 , H03G3/001 , H03G3/3047
摘要： A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.
摘要翻译：一个dB线性可变增益放大器，一种创建方法和一个系统，包括放大器; 一对可操作地连接到放大器的电阻器阵列，其中每个电阻器阵列包括MOS晶体管电阻开关; 差分斜坡发生器电路，可操作地连接到所述一对电阻器阵列; 以及由差分斜坡发生器电路产生的电压控制线，其中电压控制线可操作地连接到该对电阻器阵列中的每个MOS晶体管电阻开关。可操作地连接到每个MOS晶体管电阻开关的电压控制线的数量等于特定电阻器阵列中的电阻器的数量。差分斜坡发生器电路优选地可操作以获得自动增益控制电压并产生一系列差分斜坡电压，并将一系列差分斜坡电压施加到MOS晶体管电阻开关之一。

7. 发明授权

US07525372B2 Noise shaped n th order filter 失效
标题翻译：噪声形n级滤波器
公开(公告)号：US07525372B2
公开(公告)日：2009-04-28
申请号：US11683651
申请日：2007-03-08
申请人： Hassan Elwan , Amr Fahim , Aly Ismail , Edward Youssoufian
发明人： Hassan Elwan , Amr Fahim , Aly Ismail , Edward Youssoufian
IPC分类号： H03B1/00 , H03K5/00
CPC分类号： H03H11/04
摘要： A low noise nth order filter, system, and method includes a plurality of nested general immittance converters (GICs) operatively connected to one another in successive GIC stages; and a capacitor operatively connected to each of the GICs, wherein a first successive GIC stage begins at a first node located in between a previous GIC stage and a corresponding capacitor operatively connected to the previous GIC stage. A second successive GIC stage begins at a second node located in between the first node and the first successive GIC stage. The filter may further comprise a resistor operatively connected to at least one successive GIC stage, wherein the resistor is preferably located in between the first node and the first successive GIC stage.
摘要翻译：低噪声第n阶滤波器，系统和方法包括在连续GIC阶段中可操作地彼此连接的多个嵌套通用导纳转换器（GIC）; 以及可操作地连接到每个GIC的电容器，其中第一连续GIC级开始于位于先前GIC级与可操作地连接到先前GIC级的对应电容器之间的第一节点处。第二个连续的GIC阶段从位于第一节点和第一连续GIC阶段之间的第二节点开始。滤波器还可以包括可操作地连接到至少一个连续GIC级的电阻器，其中电阻优选地位于第一节点和第一连续GIC级之间。

8. 发明申请

US20080220737A1 NOISE SHAPED NTH ORDER FILTER 失效
标题翻译：噪音形状的第N个订单过滤器
公开(公告)号：US20080220737A1
公开(公告)日：2008-09-11
申请号：US11683651
申请日：2007-03-08
申请人： Hassan Elwan , Amr Fahim , Aly Ismail , Edward Youssoufian
发明人： Hassan Elwan , Amr Fahim , Aly Ismail , Edward Youssoufian
IPC分类号： H04B1/10
CPC分类号： H03H11/04
摘要： A low noise nth order filter, system, and method includes a plurality of nested general immittance converters (GICs) operatively connected to one another in successive GIC stages; and a capacitor operatively connected to each of the GICs, wherein a first successive GIC stage begins at a first node located in between a previous GIC stage and a corresponding capacitor operatively connected to the previous GIC stage. A second successive GIC stage begins at a second node located in between the first node and the first successive GIC stage. The filter may further comprise a resistor operatively connected to at least one successive GIC stage, wherein the resistor is preferably located in between the first node and the first successive GIC stage.
摘要翻译：低噪声第n阶滤波器，系统和方法包括在连续GIC阶段中可操作地彼此连接的多个嵌套通用导纳转换器（GIC）; 以及可操作地连接到每个GIC的电容器，其中第一连续GIC级开始于位于先前GIC级与可操作地连接到先前GIC级的对应电容器之间的第一节点处。第二个连续的GIC阶段从位于第一节点和第一连续GIC阶段之间的第二节点开始。滤波器还可以包括可操作地连接到至少一个连续GIC级的电阻器，其中电阻优选地位于第一节点和第一连续GIC级之间。

9. 发明申请

US20070296490A1 dB-linear analog variable gain amplifier (VGA) realization system and method 有权
标题翻译： dB线性模拟可变增益放大器（VGA）实现系统和方法
公开(公告)号：US20070296490A1
公开(公告)日：2007-12-27
申请号：US11472138
申请日：2006-06-21
申请人： Hassan Elwan , Amr Fahim , Aly Ismail , Edward Youssoufian
发明人： Hassan Elwan , Amr Fahim , Aly Ismail , Edward Youssoufian
IPC分类号： H03G3/20
CPC分类号： H03G7/06 , H03G1/0088 , H03G3/001 , H03G3/3047
摘要： A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.
摘要翻译：一个dB线性可变增益放大器，一种创建方法和一个系统，包括放大器; 一对可操作地连接到放大器的电阻器阵列，其中每个电阻器阵列包括MOS晶体管电阻开关; 差分斜坡发生器电路，可操作地连接到所述一对电阻器阵列; 以及由差分斜坡发生器电路产生的电压控制线，其中电压控制线可操作地连接到该对电阻器阵列中的每个MOS晶体管电阻开关。可操作地连接到每个MOS晶体管电阻开关的电压控制线的数量等于特定电阻器阵列中的电阻器的数量。差分斜坡发生器电路优选地可操作以获取自动增益控制电压并产生一系列差分斜坡电压，并将一系列差分斜坡电压施加到MOS晶体管电阻开关之一。

10. 发明申请

US20050253632A1 Low-power direct digital synthesizer with analog interpolation 有权
标题翻译：具有模拟插补功能的低功耗直接数字合成器
公开(公告)号：US20050253632A1
公开(公告)日：2005-11-17
申请号：US11186451
申请日：2005-07-20
申请人： Amr Fahim
发明人： Amr Fahim
IPC分类号： G06F1/02 , G06F1/08 , H03K3/017 , H03K5/00 , H03K5/135 , H03K5/156 , H03K23/68 , H03L7/081 , H03B19/00
CPC分类号： G06F1/022 , G06F1/08 , G06F2211/902 , H03K5/135 , H03K5/1565 , H03K2005/00032 , H03K2005/00071 , H03L7/0814
摘要： An MN counter with analog interpolation (“MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.
摘要翻译：具有模拟插值（“MNA计数器”）的MN计数器包括MN计数器，乘法器，延迟发生器和电流发生器。 MN计数器接收输入时钟信号和M和N值，使用模N累加器为每个输入时钟周期累加M，并提供具有所需频率的累加器值和计数器信号。乘法器将累加器值乘以M的倒数，并提供L位控制信号。电流发生器实现电流锁定环路，为延迟发生器提供参考电流。延迟发生器采用差分设计实现，接收计数器信号和L位控制信号，比较基于计数器和控制信号产生的差分信号，并提供输出时钟信号。输出时钟信号的前沿具有由L位控制信号和参考电流确定的可变延迟。

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