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1. 发明申请

US20080083951A1 FETS WITH SELF-ALIGNED BODIES AND BACKGATE HOLES 审中-公开
标题翻译：具有自对准体和背部孔的FET
公开(公告)号：US20080083951A1
公开(公告)日：2008-04-10
申请号：US11869766
申请日：2007-10-10
申请人： Brent Anderson , Andres Bryant , Edward Nowak , Richard Williams
发明人： Brent Anderson , Andres Bryant , Edward Nowak , Richard Williams
IPC分类号： H01L27/12
CPC分类号： H01L29/78612 , H01L29/66772 , H01L29/78621 , H01L29/78648
摘要： Embodiments of the invention disclose a design structure for a FET with a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.
摘要翻译：本发明的实施例公开了具有浅电源/漏极区域，深沟道区域，栅极叠层和被电介质包围的背栅的FET的设计结构。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

2. 发明申请

US20060240610A1 Structure and method for dual-gate FET with SOI substrate 失效
标题翻译：具有SOI衬底的双栅极FET的结构和方法
公开(公告)号：US20060240610A1
公开(公告)日：2006-10-26
申请号：US11265464
申请日：2005-11-02
申请人： Edward Nowak , Richard Williams
发明人： Edward Nowak , Richard Williams
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/42384 , H01L29/66795 , H01L2029/7858
摘要： A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized such that the gate conductor is separated into distinct gate conductor portions that are separated by the fins. These gate conductor portions include front gates and back gates. The front gates and the back gates alternate along the structure, such that each fin has a front gate on one side and a back gate on the opposite side. Then front gate wiring is formed to the front gates and back gate wiring is formed to the back gates.
摘要翻译：形成双栅极鳍型场效应晶体管（FinFET）结构的方法在绝缘体上形成硅散热片，并以与鳍片成角度的方式形成栅极导体。栅极导体横向地形成在鳍片的中心部分附近并且越过其中心部分。栅极导体被平坦化，使得栅极导体分离成由鳍分开的不同的栅极导体部分。这些栅极导体部分包括前门和后门。前门和后门沿着结构交替，使得每个鳍具有一侧的前门和相对侧上的后门。然后，前栅极布线形成于前栅极，并且后栅极布线形成于后栅极。

3. 发明申请

US20070040236A1 DISCRETE ON-CHIP SOI RESISTORS 有权
标题翻译：分离片上SOI电阻
公开(公告)号：US20070040236A1
公开(公告)日：2007-02-22
申请号：US11161911
申请日：2005-08-22
申请人： Edward Nowak , Richard Williams
发明人： Edward Nowak , Richard Williams
IPC分类号： H01L29/00
CPC分类号： H01L29/8605 , H01L27/016 , H01L27/0802 , H01L29/66166
摘要： A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.
摘要翻译：半导体电阻器，制造电阻器的方法和制造包括电阻器的IC的方法。掩埋阱形成在绝缘体上硅（SOI）晶片的硅衬底中。在埋井中形成至少一个沟槽。电阻器沿着沟槽的侧壁形成，并且在多个沟槽形成支柱的情况下，通过用成角度的植入物掺杂侧壁，在沟槽之间的支柱中形成电阻器。如果有的话，在沟槽和支柱的相对两端形成电阻触点到掩埋井。

4. 发明申请

US20060244061A1 INTEGRATED CIRCUIT (IC) WITH HIGH-Q ON-CHIP DISCRETE CAPACITORS 失效
标题翻译：集成电路（IC）与高Q片上分离电容器
公开(公告)号：US20060244061A1
公开(公告)日：2006-11-02
申请号：US10908081
申请日：2005-04-27
申请人： Edward Nowak , Richard Williams
发明人： Edward Nowak , Richard Williams
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L27/0805 , H01L29/94
摘要： A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer or a thickened portion of a surface silicon layer. The other capacitor plate may be doped polysilicon and separated from the first capacitor plate by capacitor dielectric, e.g., CVD or thermal oxide. Contacts to each of the capacitor plates directly connect and extend from the respective plates, such that direct contact is available from both plates.
摘要翻译：可以是分立电容器的半导体结构，包括具有离散这种电容器的电路和/或由这种分立电容器去耦合的片上绝缘体（SOI）集成电路（IC）和片上去耦电容器（decap））。一个电容器板可以是硅本体层中的阱（N阱或P阱）或表面硅层的增厚部分。另一个电容器板可以是掺杂多晶硅并且通过电容器电介质例如CVD或热氧化物与第一电容器板分离。与每个电容器板的接触件从相应的板直接连接和延伸，使得从两个板可以直接接触。

5. 发明申请

US20070242497A1 Dynamic control of back gate bias in a FinFET SRAM cell 失效
标题翻译： FinFET SRAM单元中背栅偏置的动态控制
公开(公告)号：US20070242497A1
公开(公告)日：2007-10-18
申请号：US11402400
申请日：2006-04-12
申请人： Rajiv Joshi , Keunwoo Kim , Edward Nowak , Richard Williams
发明人： Rajiv Joshi , Keunwoo Kim , Edward Nowak , Richard Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.
摘要翻译：本发明提供对FinFET SRAM单元中的上拉pFET的背栅极偏置的动态控制。根据本发明的方法包括向SRAM单元中的至少一个晶体管的背栅提供偏置电压，并且基于操作模式（例如，读取，半选择，写入，待机）动态地控制偏置电压，的SRAM单元。

6. 发明申请

US20070026579A1 DOPED SINGLE CRYSTAL SILICON SILICIDED EFUSE 有权
标题翻译：单晶硅晶硅胶
公开(公告)号：US20070026579A1
公开(公告)日：2007-02-01
申请号：US11161320
申请日：2005-07-29
申请人： Edward Nowak , Jed Rankin , William Tonti , Richard Williams
发明人： Edward Nowak , Jed Rankin , William Tonti , Richard Williams
IPC分类号： H01L21/84
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

7. 发明申请

US20070020837A1 HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS 失效
标题翻译：高性能电容器在平面背栅CMOS
公开(公告)号：US20070020837A1
公开(公告)日：2007-01-25
申请号：US11160999
申请日：2005-07-19
申请人： Andres Bryant , Edward Nowak , Richard Williams
发明人： Andres Bryant , Edward Nowak , Richard Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

8. 发明申请

US20060274569A1 Semiconductor device including back-gated transistors and method of fabricating the device 有权
公开(公告)号：US20060274569A1
公开(公告)日：2006-12-07
申请号：US11142248
申请日：2005-06-02
申请人： Rajiv Joshi , Keunwoo Kim , Edward Nowak , Richard Williams
发明人： Rajiv Joshi , Keunwoo Kim , Edward Nowak , Richard Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/66795 , H01L29/785
摘要： A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to the plurality of nFETs.

9. 发明授权

US10583939B2 Deployed electromagnetic radiation deflector shield (DERDS) which creates a zone of minimum radiation and magnetic/plasma effects for spacecraft and extra-planetary base station protection 有权
公开(公告)号：US10583939B2
公开(公告)日：2020-03-10
申请号：US15477115
申请日：2017-04-02
申请人： Richard Williams
发明人： Richard Williams
IPC分类号： B64G1/54 , B64G1/42
摘要： Example aspects of a deployed electromagnetic radiation deflector shield and a method for using a deployed electromagnetic radiation deflector shield are disclosed. The deployed electromagnetic radiation deflector shield can comprise a power supply; and an electromagnet configured to generate a magnetic field to deflect radiation; wherein the deployed electromagnetic radiation deflector shield is deployed at a distance away from one of a spacecraft and a base station to minimize an effect of the magnetic field on the one of the spacecraft and base station.

10. 发明授权

US09071139B2 High current switching converter for LED applications 有权
标题翻译：用于LED应用的大电流开关转换器
公开(公告)号：US09071139B2
公开(公告)日：2015-06-30
申请号：US12194411
申请日：2008-08-19
申请人： Richard Williams
发明人： Richard Williams
IPC分类号： H02M3/158 , H05B37/02 , H05B33/08
CPC分类号： H02M3/158 , H05B33/0815 , H05B37/02
摘要： A step-up switching voltage regulator includes two or more inductors and a switching network. A control circuit drives the switching network in a repeating sequence that includes: a magnetizing phase where the inductors are connected in series between an input voltage and ground; and a charge transfer phase where the inductors are connected in parallel to provide current to an output node with at least one of the inductors is connected between ground and the output node.
摘要翻译：升压开关电压调节器包括两个或更多个电感器和开关网络。控制电路以重复序列驱动交换网络，该重复序列包括：电感器串联连接在输入电压和地之间的磁化阶段; 以及电荷转移阶段，其中电感器并联连接以将电流提供给输出节点，其中至少一个电感器连接在地和输出节点之间。

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