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1. 发明授权

US08949573B2 Translation lookaside buffer structure including an output comparator 有权
标题翻译：翻译后备缓冲结构包括一个输出比较器
公开(公告)号：US08949573B2
公开(公告)日：2015-02-03
申请号：US13097286
申请日：2011-04-29
申请人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
发明人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
IPC分类号： G06F12/00 , H03K19/096 , G06F12/10 , G11C7/06
CPC分类号： H03K19/096 , G06F12/1027 , G11C7/062 , Y02D10/13
摘要： A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.
摘要翻译：处理器包括包括数据阵列和比较单元的翻译后备缓冲器（TLB）。数据阵列包括多个条目，每个条目被配置为存储相应的翻译的物理地址。响应于对TLB的给定条目的读取访问，数据阵列被配置为在特定时钟周期内输出存储在给定条目中的相应翻译的物理地址。此外，比较单元可以被配置为将由数据阵列输出的相应翻译的物理地址与多个附加地址进行比较。比较单元还可以被配置为为特定时钟周期内的每个附加地址提供命中指示。

2. 发明申请

US20120124328A1 Translation Lookaside Buffer Structure Including an Output Comparator 有权
标题翻译：包括输出比较器的翻译后备缓冲区结构
公开(公告)号：US20120124328A1
公开(公告)日：2012-05-17
申请号：US13097286
申请日：2011-04-29
申请人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
发明人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
IPC分类号： G06F12/10
CPC分类号： H03K19/096 , G06F12/1027 , G11C7/062 , Y02D10/13
摘要： A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.
摘要翻译：处理器包括包括数据阵列和比较单元的翻译后备缓冲器（TLB）。数据阵列包括多个条目，每个条目被配置为存储相应的翻译的物理地址。响应于对TLB的给定条目的读取访问，数据阵列被配置为在特定时钟周期内输出存储在给定条目中的相应翻译的物理地址。此外，比较单元可以被配置为将由数据阵列输出的相应翻译的物理地址与多个附加地址进行比较。比较单元还可以被配置为为特定时钟周期内的每个附加地址提供命中指示。

3. 发明授权

US08570824B2 Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation 有权
标题翻译：存储器具有隔离单元，用于在保持模式操作期间将存储阵列与共享I / O隔离
公开(公告)号：US08570824B2
公开(公告)日：2013-10-29
申请号：US13356786
申请日：2012-01-24
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/02
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

4. 发明申请

US20130135955A1 MEMORY DEVICE INCLUDING A RETENTION VOLTAGE RESISTOR 审中-公开
标题翻译：包含保持电压电阻的存储器件
公开(公告)号：US20130135955A1
公开(公告)日：2013-05-30
申请号：US13305796
申请日：2011-11-29
申请人： Edward M. McCombs , Kenneth W. Jones
发明人： Edward M. McCombs , Kenneth W. Jones
IPC分类号： G11C5/14
CPC分类号： G11C5/148
摘要： A mechanism for providing retention mode voltage to a memory storage array includes a resistor coupled between a power supply and a power rail of the storage array. The power rail may distribute an operating current to the bit cells of the storage array. The resistor may provide a path for current to the power rail from the power supply during operation in a retention mode. In addition, a switching device coupled between the power supply and the power rail, in parallel with the resistor, may convey operational current to the power rail from the power supply during operation in a normal mode.
摘要翻译：用于向存储器阵列提供保持模式电压的机构包括耦合在电源和存储阵列的电源轨之间的电阻器。电源轨可以将工作电流分配给存储阵列的位单元。在保持模式下，电阻器可以在操作期间从电源提供电流到电力轨的路径。此外，耦合在电源和电源轨之间的与电阻并联的开关装置可以在正常模式下操作期间将来自电源的工作电流传送到电源轨。

5. 发明授权

US08837226B2 Memory including a reduced leakage wordline driver 有权
标题翻译：存储器包括减少泄漏字线驱动器
公开(公告)号：US08837226B2
公开(公告)日：2014-09-16
申请号：US13286351
申请日：2011-11-01
申请人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
发明人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
IPC分类号： G11C11/34 , G11C8/08
CPC分类号： G11C8/08
摘要： A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.
摘要翻译：存储器包括具有减少泄漏的字线驱动器。存储器包括耦合到第一电压源的存储阵列以及包括驱动器反相器的多个字线驱动器单元。在低功率模式期间，耦合到字线电路的电压源的电压被减小或去除，而耦合到存储阵列的电压源的电压至少保持在保持电压。此外，p型晶体管耦合在阵列电压源和字线驱动器反相器的输入之间，从而将字线驱动器反相器的输出保持在低逻辑电平以防止意外的字线触发。

6. 发明授权

US08553472B2 Memory with a shared I/O including an output data latch having an integrated clamp 有权
标题翻译：具有共享I / O的存储器，包括具有集成钳位的输出数据锁存器
公开(公告)号：US08553472B2
公开(公告)日：2013-10-08
申请号：US13311340
申请日：2011-12-05
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
摘要翻译：存储器包括在多个存储阵列之间共享的共享I / O单元，提供来自阵列的输出数据。共享I / O包括具有集成输出钳位的输出锁存器。 I / O单元可以被配置为经由数据输出信号路径从存储阵列提供输出数据。 I / O单元包括输出锁存器，其被配置为响应于掉电状态来迫使数据输出信号路径上的有效逻辑电平。

7. 发明授权

US08358152B2 Integrated circuit including pulse control logic having shared gating control 有权
公开(公告)号：US08358152B2
公开(公告)日：2013-01-22
申请号：US13097206
申请日：2011-04-29
申请人： Edward M. McCombs
发明人： Edward M. McCombs
IPC分类号： H03K19/00
CPC分类号： H03K19/096 , G06F12/1027 , G11C7/062 , Y02D10/13
摘要： An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

8. 发明申请

US20130141988A1 MEMORY WITH A SHARED I/O INCLUDING AN OUTPUT DATA LATCH HAVING AN INTEGRATED CLAMP 有权
标题翻译：具有共享I / O的存储器，包括具有集成钳位的输出数据线
公开(公告)号：US20130141988A1
公开(公告)日：2013-06-06
申请号：US13311340
申请日：2011-12-05
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
摘要翻译：存储器包括在多个存储阵列之间共享的共享I / O单元，提供来自阵列的输出数据。共享I / O包括具有集成输出钳位的输出锁存器。 I / O单元可以被配置为经由数据输出信号路径从存储阵列提供输出数据。 I / O单元包括输出锁存器，其被配置为响应于掉电状态来迫使数据输出信号路径上的有效逻辑电平。

9. 发明授权

US08400864B1 Mechanism for peak power management in a memory 有权
标题翻译：记忆中峰值功率管理的机制
公开(公告)号：US08400864B1
公开(公告)日：2013-03-19
申请号：US13286365
申请日：2011-11-01
申请人： Edward M. McCombs
发明人： Edward M. McCombs
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/12 , G11C8/18
摘要： A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block.
摘要翻译：用于管理包括子阵列块的存储器阵列中的峰值功率的机制可以通过将字线信号激活交错到每个子阵列块来减少与读取和写入操作相关联的峰值电流。特别地，每个子阵列块内的字线单元可以向每个子阵列块产生字线信号，使得一个子阵列块的读取字线信号不会同时从一个逻辑电平转换到另一个逻辑电平作为另一个子阵列块的写字线。此外，字线单元可以向每个子阵列块产生字线信号，使得给定子阵列块的读取字线不会与另一个逻辑电平的读取字线信号同时从一个逻辑电平转换到另一个逻辑电平子阵列块。

10. 发明申请

US20120203480A1 POWER ESTIMATION IN AN INTEGRATED CIRCUIT DESIGN FLOW 有权
标题翻译：集成电路设计流程中的功率估计
公开(公告)号：US20120203480A1
公开(公告)日：2012-08-09
申请号：US13183335
申请日：2011-07-14
申请人： Jason A. Frerich , Christopher M. Goertz , Edward M. McCombs
发明人： Jason A. Frerich , Christopher M. Goertz , Edward M. McCombs
IPC分类号： G06F19/00
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Power estimates for an integrated circuit may be obtained without having to individually enter monitor statements at hierarchical levels in a design. The current, or consumed power may be considered at the transistor level throughout the entire circuit, even when the circuit is divided into hierarchical modules. Current, or power measurements may be obtained after a circuit has been synthesized and an extracted transistor-level netlist has been created. Separate netlists may be created for different modules, and estimate results collected from the different modules, since current measurements are performed at the transistor level. To accurately estimate the power consumption, the current flowing through transistors that are connected to power rails in the netlist may be measured during circuit simulation. This may be accomplished via measurement statements created for these transistors, and placed in a simulation input file, by a script or program, for example. Only the currents flowing through these transistors need to be measured to account for all the current provided from the power sources in the design.
摘要翻译：可以获得集成电路的功率估计，而无需在设计中分层输入监视语句。即使将电路划分为分层模块，电流或消耗功率也可以在整个电路的晶体管级考虑。可以在电路合成并且已经创建提取的晶体管级网表之后获得电流或功率测量值。可以为不同的模块创建单独的网表，并估计从不同模块收集的结果，因为电流测量在晶体管级执行。为了精确地估计功耗，可以在电路仿真期间测量流过连接到网表中的电力轨的晶体管的电流。这可以通过为这些晶体管创建的测量语句来实现，并且通过脚本或程序放置在模拟输入文件中。需要测量流过这些晶体管的电流，以考虑设计中从电源提供的所有电流。

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