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1. 发明授权

US08570824B2 Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation 有权
标题翻译：存储器具有隔离单元，用于在保持模式操作期间将存储阵列与共享I / O隔离
公开(公告)号：US08570824B2
公开(公告)日：2013-10-29
申请号：US13356786
申请日：2012-01-24
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/02
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

2. 发明申请

US20130141988A1 MEMORY WITH A SHARED I/O INCLUDING AN OUTPUT DATA LATCH HAVING AN INTEGRATED CLAMP 有权
标题翻译：具有共享I / O的存储器，包括具有集成钳位的输出数据线
公开(公告)号：US20130141988A1
公开(公告)日：2013-06-06
申请号：US13311340
申请日：2011-12-05
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
摘要翻译：存储器包括在多个存储阵列之间共享的共享I / O单元，提供来自阵列的输出数据。共享I / O包括具有集成输出钳位的输出锁存器。 I / O单元可以被配置为经由数据输出信号路径从存储阵列提供输出数据。 I / O单元包括输出锁存器，其被配置为响应于掉电状态来迫使数据输出信号路径上的有效逻辑电平。

3. 发明授权

US08553472B2 Memory with a shared I/O including an output data latch having an integrated clamp 有权
标题翻译：具有共享I / O的存储器，包括具有集成钳位的输出数据锁存器
公开(公告)号：US08553472B2
公开(公告)日：2013-10-08
申请号：US13311340
申请日：2011-12-05
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
摘要翻译：存储器包括在多个存储阵列之间共享的共享I / O单元，提供来自阵列的输出数据。共享I / O包括具有集成输出钳位的输出锁存器。 I / O单元可以被配置为经由数据输出信号路径从存储阵列提供输出数据。 I / O单元包括输出锁存器，其被配置为响应于掉电状态来迫使数据输出信号路径上的有效逻辑电平。

4. 发明申请

US20130188435A1 MEMORY HAVING ISOLATION UNITS FOR ISOLATING STORAGE ARRAYS FROM A SHARED I/O DURING RETENTION MODE OPERATION 有权
标题翻译：在保留模式操作期间从分享的I / O分离存储阵列的隔离单元的内存
公开(公告)号：US20130188435A1
公开(公告)日：2013-07-25
申请号：US13356786
申请日：2012-01-24
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

5. 发明申请

US20130135955A1 MEMORY DEVICE INCLUDING A RETENTION VOLTAGE RESISTOR 审中-公开
标题翻译：包含保持电压电阻的存储器件
公开(公告)号：US20130135955A1
公开(公告)日：2013-05-30
申请号：US13305796
申请日：2011-11-29
申请人： Edward M. McCombs , Kenneth W. Jones
发明人： Edward M. McCombs , Kenneth W. Jones
IPC分类号： G11C5/14
CPC分类号： G11C5/148
摘要： A mechanism for providing retention mode voltage to a memory storage array includes a resistor coupled between a power supply and a power rail of the storage array. The power rail may distribute an operating current to the bit cells of the storage array. The resistor may provide a path for current to the power rail from the power supply during operation in a retention mode. In addition, a switching device coupled between the power supply and the power rail, in parallel with the resistor, may convey operational current to the power rail from the power supply during operation in a normal mode.
摘要翻译：用于向存储器阵列提供保持模式电压的机构包括耦合在电源和存储阵列的电源轨之间的电阻器。电源轨可以将工作电流分配给存储阵列的位单元。在保持模式下，电阻器可以在操作期间从电源提供电流到电力轨的路径。此外，耦合在电源和电源轨之间的与电阻并联的开关装置可以在正常模式下操作期间将来自电源的工作电流传送到电源轨。

6. 发明授权

US5610543A Delay locked loop for detecting the phase difference of two signals having different frequencies 失效
标题翻译：用于检测具有不同频率的两个信号的相位差的延迟锁定环
公开(公告)号：US5610543A
公开(公告)日：1997-03-11
申请号：US417155
申请日：1995-04-04
申请人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
发明人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
IPC分类号： G11C7/22 , H03L7/06 , H03K5/13
CPC分类号： G11C7/22
摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.
摘要翻译：延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步，。塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

7. 发明授权

US5400274A Memory having looped global data lines for propagation delay matching 失效
标题翻译：具有循环全局数据线以用于传播延迟匹配的存储器
公开(公告)号：US5400274A
公开(公告)日：1995-03-21
申请号：US236845
申请日：1994-05-02
申请人： Kenneth W. Jones , Lawrence F. Childs
发明人： Kenneth W. Jones , Lawrence F. Childs
IPC分类号： G11C7/10 , G11C5/06
CPC分类号： G11C7/10
摘要： A synchronous memory (50) having a looped global data line (80) reduces a difference between minimum and maximum propagation delays between different locations in a memory array (51) during a read cycle of the memory (50). The looped global data line (80) has a first portion (80') and a second portion (80"). The first portion (80') extends along an edge of the memory array (51) in a direction substantially parallel to a direction of the word lines of the array (51). Sense amplifiers (73-78) are coupled to the first portion (80') of the looped global data line (80). At one end of the array (51), the second portion (80") of the looped global data line extends back in an opposite direction to the first portion (80') and is coupled to output data circuits (84). Reducing the difference in propagation delays improves noise margins and allows increased operating speed.
摘要翻译：具有循环全局数据线（80）的同步存储器（50）在存储器（50）的读取周期期间减少存储器阵列（51）中的不同位置之间的最小和最大传播延迟之间的差异。环路全局数据线（80）具有第一部分（80'）和第二部分（80“）。第一部分（80'）沿着与阵列（51）的字线的方向基本平行的方向沿着存储器阵列（51）的边缘延伸。感测放大器（73-78）耦合到环路全局数据线（80）的第一部分（80'）。在阵列（51）的一端，环形全局数据线的第二部分（80“）在与第一部分（80'）相反的方向上延伸并耦合到输出数据电路（84）。降低传播延迟的差异可以提高噪音容限，并提高运行速度。

8. 发明授权

US5217592A Electrophoresis and vacuum molecular transfer apparatus 失效
标题翻译：电泳和真空分子转移装置
公开(公告)号：US5217592A
公开(公告)日：1993-06-08
申请号：US696316
申请日：1991-04-30
申请人： Kenneth W. Jones
发明人： Kenneth W. Jones
IPC分类号： B01D57/02 , G01N27/447
CPC分类号： B01D57/02 , G01N27/44717
摘要： An apparatus which includes the combination of a submarine gel tank, for the electrophoresic separation of, for example, nucleic acid molecules on agarose slab gels, with a vacuum applying means which transfers the separated molecules from the gel, without further handling, to a filter membrane by means of a controlled vacuum.
摘要翻译：一种装置，其包括用于电泳分离琼脂糖凝胶上的核酸分子的潜艇凝胶罐与真空施加装置的组合，所述真空施加装置将分离出的分子从凝胶转移而不进一步处理到过滤器膜通过受控真空。

9. 发明授权

US4846290A Underreamer with revolving diamond cutter elements 失效
标题翻译：旋转金刚石刀片元素的深深
公开(公告)号：US4846290A
公开(公告)日：1989-07-11
申请号：US207684
申请日：1988-06-16
申请人： Kenneth W. Jones
发明人： Kenneth W. Jones
IPC分类号： E21B10/12 , E21B10/22 , E21B10/34 , E21B10/50 , E21B10/52 , E21B10/56 , E21B10/567 , E21B10/62
CPC分类号： E21B10/52 , E21B10/12 , E21B10/22 , E21B10/34 , E21B10/50 , E21B10/567 , E21B10/62
摘要： A sub-surface borehole underreamer is disclosed having freely rotatable precessing diamond cutters attached to extendable arms connected to the body of the underreamer. The diamond cutting face is skewed to a degree that tangential contact of the peripheral edge of the diamond cutter causes the rotating cutter to precess as the underreamer body is rotated by a drill string.
摘要翻译：公开了一种子表面钻孔扩孔器，其具有可自由旋转的进给金刚石切割器，该切割器附接到连接到扩孔器主体的可伸缩臂。金刚石切割面歪斜到金刚石切割器的周缘的切向接触使得旋转切割器在钻头主体被钻柱旋转时进入。

10. 外观设计

USD295133S Scoop for french fries 失效
公开(公告)号：USD295133S
公开(公告)日：1988-04-12
申请号：US747803
申请日：1985-06-24
申请人： Kenneth W. Jones
设计人： Kenneth W. Jones

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