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    • 4. 发明授权
    • Dynamic phase alignment of a clock and data signal using an adjustable clock delay line
    • 使用可调时钟延迟线对时钟和数据信号进行动态相位对准
    • US07034597B1
    • 2006-04-25
    • US10933742
    • 2004-09-03
    • Shan MoJames R. BrownRichard A. MosherRobert S. Kirk
    • Shan MoJames R. BrownRichard A. MosherRobert S. Kirk
    • H03H11/26
    • H04L7/0337H03L7/0814
    • A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.
    • 一种动态相位调整电路,其包括接收时钟输入信号的多抽头延迟线。 多抽头延迟线包括可调节的初始部分和可调节部分之后的最后部分。 许多寄存器收到相同的数据。 然而,使得寄存器采样的时钟信号从多抽头延迟线的最后部分中的对应延迟元件接收。 边缘检测和数据判定电路从每个寄存器接收采样的数据值。 采样分辨率比基于PLL的动态相位调整电路得到改进,因为时钟信号使用延迟元件进行延迟,延迟元件可以用较小的延迟进行。 此外,电路不包含过多的电路元件,从而允许动态相位调整电路容纳在小的区域中。