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1. 发明授权

US4981909A Plasma-resistant polymeric material, preparation thereof, and use thereof 失效
标题翻译：耐等离子体聚合材料，其制备及其用途
公开(公告)号：US4981909A
公开(公告)日：1991-01-01
申请号：US241281
申请日：1988-09-07
申请人： Edward D. Babich , Michael Hatzakis , Scott L. Jacobs , Juri R. Parasczcak , Jane M. Shaw , David F. Witman
发明人： Edward D. Babich , Michael Hatzakis , Scott L. Jacobs , Juri R. Parasczcak , Jane M. Shaw , David F. Witman
IPC分类号： G03F7/038 , G03F7/26
CPC分类号： G03F7/038 , G03F7/265
摘要： Plasma-resistant polymeric materials are prepared by reacting a polymeric material containing reactive hydrogen functional groups with a multifunctional organometallic material containing at least two functional groups which are reactive with the reactive hydrogen functional groups of the polymeric material, such as hexamethylcyclotrisilazane.
摘要翻译：通过使含有反应性氢官能团的聚合材料与含有至少两个与聚合物材料的反应性氢官能团（例如六甲基环三硅氮烷）反应的官能团的多官能有机金属材料反应来制备等离子体的聚合材料。

2. 发明授权

US4782008A Plasma-resistant polymeric material, preparation thereof, and use thereof 失效
标题翻译：耐等离子体聚合材料，其制备及其用途
公开(公告)号：US4782008A
公开(公告)日：1988-11-01
申请号：US713509
申请日：1985-03-19
申请人： Edward D. Babich , Michael Hatzakis , Scott L. Jacobs , Juri R. Parasczcak , Jane M. Shaw , David F. Witman
发明人： Edward D. Babich , Michael Hatzakis , Scott L. Jacobs , Juri R. Parasczcak , Jane M. Shaw , David F. Witman
IPC分类号： C08L61/00 , C08K5/549 , C08L33/00 , C08L33/02 , C08L61/04 , C08L61/06 , G03C1/00 , G03C1/72 , G03F7/004 , G03F7/038 , G03F7/26 , G03F7/38 , H01L21/027 , G03C5/00 , C08F8/00 , C08L83/00
CPC分类号： G03F7/038 , G03F7/265
摘要： Plasma-resistant polymeric materials are prepared by reacting a polymeric material containing reactive hydrogen functional groups with a multifunctional organometallic material containing at least two functional groups which are reactive with the reactive hydrogen functional groups of the polymeric material, such as hexamethylcyclotrisilazane.
摘要翻译：通过使含有反应性氢官能团的聚合物材料与含有至少两个与聚合物材料的反应性氢官能团（例如六甲基环三硅氮烷）反应的官能团的多官能有机金属材料反应来制备等离子体聚合材料。

3. 发明授权

US5192716A Method of making a extended integration semiconductor structure 失效
标题翻译：制造扩展集成半导体结构的方法
公开(公告)号：US5192716A
公开(公告)日：1993-03-09
申请号：US735340
申请日：1991-07-24
申请人： Scott L. Jacobs
发明人： Scott L. Jacobs
IPC分类号： H01L21/68 , H01L23/538
CPC分类号： H01L21/6835 , H01L23/5383 , H01L23/5387 , H01L2221/68345 , H01L2924/0002 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , Y10T29/49004 , Y10T29/4913
摘要： A low cost, lightweight, fast, dense and reliable extended integration semiconductor structure is provided by forming a thin film multilayer wiring decal on a support substrate and aligning and attaching one or more integrated chips to the decal. A support ring is attached to the decal surrounding the aligned and attached integrated substrate, and the support substrate is removed. Reach-through vias connect the decal wiring to the chips.
摘要翻译：通过在支撑衬底上形成薄膜多层布线贴花并将一个或多个集成芯片对准并附着到贴花来提供低成本，轻量，快速，致密和可靠的扩展集成半导体结构。将支撑环附接到围绕对准和附接的集成基板的贴花，并且移除支撑基板。到达通孔将贴花线连接到芯片。

4. 发明授权

US4828964A Polyimide formulation for forming a patterned film on a substrate 失效
标题翻译：用于在基材上形成图案化膜的聚酰亚胺制剂
公开(公告)号：US4828964A
公开(公告)日：1989-05-09
申请号：US93360
申请日：1987-09-04
申请人： William R. Brunsvold , Willard E. Conley , Scott L. Jacobs , George L. Mack , David P. Merritt , Ann M. Uptmor
发明人： William R. Brunsvold , Willard E. Conley , Scott L. Jacobs , George L. Mack , David P. Merritt , Ann M. Uptmor
IPC分类号： G03F7/09
CPC分类号： G03F7/094 , G03F7/091
摘要： A composition for use in a process for the deposition of patterned thin metal films on integrated circuit substrates, the composition comprising an admixture of a thermoplastic polyimide resin and a coumarin dye dissolved in a substituted phenol solvent. Optionally a polar solvent having a boiling point greater than 160.degree. C. and a low boiling organic compound (70.degree.-150.degree. C.) may be incorporated in the composition.
摘要翻译：一种用于在集成电路基板上沉积图案化的金属薄膜的方法的组合物，该组合物包含溶解在取代的苯酚溶剂中的热塑性聚酰亚胺树脂和香豆素染料的混合物。任选地，可以将沸点大于160℃的极性溶剂和低沸点有机化合物（70-150℃）并入组合物中。

5. 发明授权

US5325265A High performance integrated circuit chip package 失效
标题翻译：高性能集成电路芯片封装
公开(公告)号：US5325265A
公开(公告)日：1994-06-28
申请号：US819571
申请日：1992-01-07
申请人： Iwona Turlik , Arnold Reisman , Deepak Nayak , Lih-Tyng Hwang , Giora Dishon , Scott L. Jacobs , Robert F. Darveaux , Neil M. Poley
发明人： Iwona Turlik , Arnold Reisman , Deepak Nayak , Lih-Tyng Hwang , Giora Dishon , Scott L. Jacobs , Robert F. Darveaux , Neil M. Poley
IPC分类号： H01L23/373 , H01L23/473 , H01L23/538 , H01L25/065 , H05K7/20
CPC分类号： H01L24/32 , H01L23/3736 , H01L23/473 , H01L23/5383 , H01L25/0655 , H01L2224/16225 , H01L2224/27013 , H01L2224/73253 , H01L2224/73257 , H01L2224/83051 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15312 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/351
摘要： A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.
摘要翻译：高性能集成电路芯片封装包括：支撑基板，其具有从一个面向其相对面延伸的导体，以及在该支撑基板的相对面上的多层布线基板，用于将安装在其上的芯片彼此连接并连接至导体。散热器包括在其一个面上的微通道，其中导热垫将散热片的一个面与芯片的暴露的背面连接起来，以提供具有高散热性的高密度芯片封装。支撑衬底和散热器可以由具有热膨胀匹配硅的材料块形成。垫子是低熔点焊料，优选纯铟，并且足够厚以吸收热应力，但是足够薄以有效地将热量从芯片传导到散热器。

6. 发明授权

US4811082A High performance integrated circuit packaging structure 失效
标题翻译：高性能集成电路封装结构
公开(公告)号：US4811082A
公开(公告)日：1989-03-07
申请号：US929946
申请日：1986-11-12
申请人： Scott L. Jacobs , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann
发明人： Scott L. Jacobs , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann
IPC分类号： H01L23/52 , H01L23/538 , H01L27/00 , H01L39/02 , H01L23/02 , H01L23/12
CPC分类号： H01L23/5383 , H01L23/538 , H01L2224/16225 , H01L2924/09701 , H01L2924/3011
摘要： A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.
摘要翻译：一种高速，高性能的集成电路封装结构，可用于仿真晶圆级整合结构。优选实施例包括具有基底基板的插入件，其上具有交替的绝缘层和导电层，其中多个导电层是用于在封装中保持极低噪声水平的布线装置。布线装置的低噪声电平和低电阻和电容允许多个分立的半导体段通过集成电路封装安装在其上并以与租赁规则要求相比大大减少的数量的驱动器和接收器相互连接。本发明的每个集成电路结构在性能上模拟大的芯片或晶片级整合结构，而不必产生大的芯片或晶片，并且没有冗余方案。多个这些集成电路封装结构通过贴花组合形成计算机或其一部分的中央处理单元。在替代的优选实施例中，插入器的基底衬底由硅制成，并且在其中形成任何所需的驱动器，从而基本上消除了对每个分立半导体段上的任何驱动器的需要。

7. 发明授权

US4817093A Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure 失效
标题翻译：划分，测试和诊断VLSI多芯片封装及相关结构的方法
公开(公告)号：US4817093A
公开(公告)日：1989-03-28
申请号：US64976
申请日：1987-06-18
申请人： Scott L. Jacobs , Maurice T. McMahon, Jr. , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
发明人： Scott L. Jacobs , Maurice T. McMahon, Jr. , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/27 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/318385 , G06F11/27
摘要： A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

8. 发明申请

US20120097971A1 CONTIGUOUS AND VIRTUALLY CONTIGUOUS AREA EXPANSION OF SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：半导体基板的连续和虚拟连续区域扩展
公开(公告)号：US20120097971A1
公开(公告)日：2012-04-26
申请号：US13281356
申请日：2011-10-25
申请人： Scott L. Jacobs
发明人： Scott L. Jacobs
IPC分类号： H01L29/20 , H01L21/306 , H01L29/06
CPC分类号： H01L29/2003 , H01L29/0657 , H01L31/035281 , H01L31/0392 , H01L31/0504 , H01L33/20 , Y02E10/50
摘要： Substrates are processed, with a high degree of topography, to produce a variety of semiconductors or other devices and are then stretched out, substantially flat, to achieve a significant increase in surface area. Devices made from a contiguous structure of a single, active crystalline material or from non-contiguous structures of multiple materials, such as a combination of dielectrics, thin film metals and active crystalline semiconductors, are fabricated by utilizing anisotropically etched, high aspect ratio configurations of the active material. The structure is then stretched out to achieve a significant increase in surface area, thereby enabling a substantial reduction in the cost of the substrate materials per unit area in the final product.
摘要翻译：底物被处理，具有高度的形貌，以产生各种半导体或其它装置，然后被拉伸，基本平坦，以达到显着增加的表面积。通过利用各向异性蚀刻的高纵横比构造来制造由单个活性结晶材料的连续结构或多个材料的不连续结构（例如电介质，薄膜金属和有源晶体半导体的组合）制成的器件活性物质。然后将结构拉伸以实现表面积的显着增加，从而能够显着降低最终产品中每单位面积的基材的成本。

9. 发明授权

US06294407B1 Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same 失效
标题翻译：包括其中具有导电通孔的薄膜贴花和介电粘合剂层的微电子封装及其制造方法
公开(公告)号：US06294407B1
公开(公告)日：2001-09-25
申请号：US09306463
申请日：1999-05-05
申请人： Scott L. Jacobs
发明人： Scott L. Jacobs
IPC分类号： H01L2144
CPC分类号： H01L21/4857 , H01L21/4839 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2924/01078 , H01L2924/01322 , H01L2924/07811 , H01L2924/15174 , H01L2924/15311 , H05K3/0058 , H05K3/321 , H05K3/368 , H05K3/467 , H05K3/4682 , H05K2201/10378 , H05K2201/10719 , H05K2203/016 , H05K2203/0191 , H05K2203/0531 , H05K2203/063 , H01L2924/00
摘要： Microelectronic packages may be fabricated by forming a release layer on a process substrate. A thin film decal is formed on the release layer. The thin film decal includes first and second opposing decal faces, first decal input/output pads on the first decal face, second decal input/output pads on the second decal face and at least one internal wiring layer that electrically connects at least one of the first and second decal input/output pads. The first decal input/output pads are adjacent the release layer and the second decal input/output pads are remote from the release layer. A dielectric adhesive layer is then formed on the second decal face. The dielectric adhesive layer includes first and second opposing dielectric layer faces and conductive vias therein that extend between the first and second opposing dielectric adhesive layer faces. The first dielectric adhesive layer face is adjacent the second decal face and the second adhesive dielectric layer face is remote from the second decal face, such that at least one of the conductive vias electrically connects to at least one of the second decal input/output pads. The dielectric adhesive layer second face is then adhesively bonded to a second level substrate, such as a printed circuit board, that includes second level substrate input/output pads on a face thereof, such that at least one of the conductive vias electrically connects to at least one of the second level substrate input/output pads. The release layer is processed, for example dissolved, to thereby release the process substrate from on the first face of the thin film decal. A first level substrate, such as an integrated circuit chip, is then bonded to the first face of the thin film decal, for example by solder bump reflow.
摘要翻译：微电子封装可以通过在工艺衬底上形成剥离层来制造。在剥离层上形成薄膜贴花。薄膜贴花包括第一和第二相对的贴花面，第一贴花面上的第一贴花输入/输出垫，第二贴花面上的第二贴花输入/输出垫和至少一个内部布线层，其将至少一个第一和第二贴花输入/输出垫。第一贴花输入/输出垫与释放层相邻，第二贴花输入/输出垫远离释放层。然后在第二贴花面上形成介电粘合剂层。电介质粘合剂层包括第一和第二相对的电介质层面和其中的导电通孔，其在第一和第二相对介电粘合剂层面之间延伸。第一介电粘合剂层面与第二贴花面相邻，第二粘合介电层面远离第二贴花面，使得至少一个导电通孔电连接至第二贴花输入/输出垫中的至少一个。然后将电介质粘合剂层第二面粘合到诸如印刷电路板的第二层基板上，该印刷电路板包括其表面上的第二级基板输入/输出焊盘，使得至少一个导电通孔电连接到至少一个第二级基板输入/输出焊盘。处理剥离层，例如溶解，从而从薄膜贴花的第一面上释放处理衬底。然后，诸如集成电路芯片的第一级衬底例如通过焊料回流焊接到薄膜贴花的第一面上。

10. 发明授权

US5055907A Extended integration semiconductor structure with wiring layers 失效
标题翻译：具有布线层的扩展集成半导体结构
公开(公告)号：US5055907A
公开(公告)日：1991-10-08
申请号：US301972
申请日：1989-01-25
申请人： Scott L. Jacobs
发明人： Scott L. Jacobs
IPC分类号： H01L21/68 , H01L23/538
CPC分类号： H01L21/6835 , H01L23/5383 , H01L23/5387 , H01L2221/68345 , H01L2924/0002 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： A low cost, lightweight, fast, dense and reliable extended integration semiconductor structure is provided by forming a thin film multilayer wiring decal on a support substrate and aligning and attaching one or more integrated chips to the decal. A support ring is attached to the decal surrounding the aligned and attached integrated substrate, and the support substrate is removed. Reach-through vias connect the decal wiring to the chips.
摘要翻译：通过在支撑衬底上形成薄膜多层布线贴花并将一个或多个集成芯片对准并附着到贴花来提供低成本，轻量，快速，致密和可靠的扩展集成半导体结构。将支撑环附接到围绕对准和附接的集成基板的贴花，并且移除支撑基板。到达通孔将贴花线连接到芯片。

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