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1. 发明授权

US4817093A Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure 失效
标题翻译：划分，测试和诊断VLSI多芯片封装及相关结构的方法
公开(公告)号：US4817093A
公开(公告)日：1989-03-28
申请号：US64976
申请日：1987-06-18
申请人： Scott L. Jacobs , Maurice T. McMahon, Jr. , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
发明人： Scott L. Jacobs , Maurice T. McMahon, Jr. , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/27 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/318385 , G06F11/27
摘要： A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

2. 发明授权

US4581739A Electronically selectable redundant array (ESRA) 失效
标题翻译：电子可选冗余阵列（ESRA）
公开(公告)号：US4581739A
公开(公告)日：1986-04-08
申请号：US597958
申请日：1984-04-09
申请人： Maurice T. McMahon, Jr.
发明人： Maurice T. McMahon, Jr.
IPC分类号： G06F12/16 , G11C29/00 , G11C29/04 , G11C29/32 , G06F11/20
CPC分类号： G11C29/789 , G11C29/32
摘要： The disclosure is directed to an electronically selectable redundant array or memory technique and circuitry. More particularly the invention utilizes Level Sensitive Scan Design (LSSD) circuitry with limited modification to perform the additional function of selecting a redundant word (or words) in a memory chip containing at least one defective word. The correction mechanism is independent of which word line (or word lines) is bad, and is therefore independent of I/O pin (or pad) connection of the array chip.
摘要翻译：本公开涉及电子可选择的冗余阵列或存储器技术和电路。更具体地，本发明利用具有有限修改的级别敏感扫描设计（LSSD）电路来执行在包含至少一个缺陷字的存储器芯片中选择冗余字（或多个字）的附加功能。校正机制独立于哪个字线（或字线）不好，因此与阵列芯片的I / O引脚（或焊盘）连接无关。

3. 发明授权

US4220917A Test circuitry for module interconnection network 失效
标题翻译：模块互连网络的测试电路
公开(公告)号：US4220917A
公开(公告)日：1980-09-02
申请号：US929480
申请日：1978-07-31
申请人： Maurice T. McMahon, Jr.
发明人： Maurice T. McMahon, Jr.
IPC分类号： G01R31/02 , G01R31/28 , H01L21/66 , H01L23/52 , H01L23/58 , G01R31/22
CPC分类号： H01L22/32 , G01R31/024 , G01R31/2884 , H01L2224/16225 , H01L2924/15192 , H01L2924/3011
摘要： This specification deals with testing of a network of electrical interconnections between chips mounted on an insulative substrate of a module and between the chips and the input and output pins of the module. Each of the mounted chips contains masking circuits which can be activated to prevent controlling signals from the outputs of logic circuits on the chip from being transmitted off the chip and into the interconnection network. Also each of the chips contains emitter follower circuits that logically connect all the chip input terminals to a common output terminal of the chip. In testing the mask circuits are activated. Then potential levels are selectively applied to a plurality of test points in the interconnection network and differences in potential level between these test points and/or between the points and one or more of the common terminals are determined.
摘要翻译：该规范涉及安装在模块的绝缘基板上的芯片与芯片与模块的输入和输出引脚之间的电互连网络的测试。每个安装的芯片都包含可被激活的屏蔽电路，以防止来自芯片上的逻辑电路的输出的信号从芯片传输到互连网络。此外，每个芯片都包含射极跟随器电路，逻辑上将所有芯片输入端子连接到芯片的公共输出端子。在测试中，屏蔽电路被激活。然后将电位电平选择性地应用于互连网络中的多个测试点，并且确定这些测试点之间和/或在点与一个或多个公共终端之间的电位电平的差异。

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