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1. 发明授权

US09342096B2 Modular structure for processing data 有权
标题翻译：用于处理数据的模块化结构
公开(公告)号：US09342096B2
公开(公告)日：2016-05-17
申请号：US13637061
申请日：2011-03-16
申请人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
发明人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
IPC分类号： G06F1/12 , G06F1/10 , G06F1/14
CPC分类号： G06F1/10 , G06F1/14
摘要： A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.
摘要翻译：用于数据处理系统的电路装置被配置为处理多个模块中的数据。电路布置被配置为使得每个模块被提供有至少一个时钟脉冲，时基和至少一个附加物理变量的基极。电路装置还包括中央路由单元，多个模块耦合到该中央路由单元，多个模块可以经由该中央路由单元基于时基和/或其他物理变量的基础周期性地在它们之间交换数据。每个模块独立配置并且与多个模块中的其他模块并行配置，以便处理数据。电路装置采用相应的方法。

2. 发明申请

US20130227331A1 Modular Structure for Processing Data 有权
标题翻译：处理数据的模块化结构
公开(公告)号：US20130227331A1
公开(公告)日：2013-08-29
申请号：US13637061
申请日：2011-03-16
申请人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
发明人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
IPC分类号： G06F1/10
CPC分类号： G06F1/10 , G06F1/14
摘要： A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.
摘要翻译：用于数据处理系统的电路装置被配置为处理多个模块中的数据。电路布置被配置为使得每个模块被提供有至少一个时钟脉冲，时基和至少一个附加物理变量的基极。电路装置还包括中央路由单元，多个模块耦合到该中央路由单元，多个模块可以经由该中央路由单元基于时基和/或其他物理变量的基础周期性地在它们之间交换数据。每个模块独立配置并且与多个模块中的其他模块并行配置，以便处理数据。电路装置采用相应的方法。

3. 发明申请

US20130111189A1 Circuit Arrangement for a Data Processing System and Method for Data Processing 有权
标题翻译：数据处理系统的电路布置和数据处理方法
公开(公告)号：US20130111189A1
公开(公告)日：2013-05-02
申请号：US13638125
申请日：2011-03-18
申请人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
IPC分类号： G06F15/76
CPC分类号： G06F15/76 , G06F1/04
摘要： A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.
摘要翻译：用于数据处理系统的电路装置被配置为处理多个模块中的数据。电路布置被配置为为多个模块中的每一个提供时钟以及时基和/或至少一个另外的物理量的基极。电路装置还包括中央路由单元，其连接到多个模块中的若干个。通过中央路由单元，模块可以基于时基和/或基于至少一个其他物理量周期性地交换数据。多个模块被配置为独立于和并行地处理数个模块的其他模块的数据。

4. 发明授权

US09501370B2 Timer module and method for testing output signals of a timer module 有权
标题翻译：定时器模块和测试定时器模块输出信号的方法
公开(公告)号：US09501370B2
公开(公告)日：2016-11-22
申请号：US13637130
申请日：2011-03-17
申请人： Eberhard Boehl , Stephen Schmitt , Juergen Hanisch
发明人： Eberhard Boehl , Stephen Schmitt , Juergen Hanisch
IPC分类号： G06F11/00 , G06F11/16 , G06F1/04
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/1608 , G06F11/1679
摘要： In a timer module having at least two output channels, the at least two output channels are configurable in such a way that they generate redundant output signals, and the generation of the redundant output signals begins synchronously. In addition, the timer module has provides a comparison of the redundant output signals by an EXOR logic operation and stores a result of the EXOR logic operation in a way that allows the result to be retained for an erroneous comparison until it is reset by an access.
摘要翻译：在具有至少两个输出通道的定时器模块中，所述至少两个输出通道可以以这样的方式配置，使得它们产生冗余输出信号，并且冗余输出信号的产生同步开始。此外，定时器模块通过EXOR逻辑运算提供了冗余输出信号的比较，并且以允许结果被保留以进行错误比较的方式存储EXOR逻辑运算的结果，直到其被访问重置为止。

5. 发明授权

US09367516B2 Circuit arrangement for a data processing system and method for data processing 有权
标题翻译：数据处理系统的电路布置和数据处理方法
公开(公告)号：US09367516B2
公开(公告)日：2016-06-14
申请号：US13638125
申请日：2011-03-18
申请人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
IPC分类号： G06F1/12 , G06F15/76 , G06F1/04
CPC分类号： G06F15/76 , G06F1/04
摘要： A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.
摘要翻译：用于数据处理系统的电路装置被配置为处理多个模块中的数据。电路布置被配置为为多个模块中的每一个提供时钟以及时基和/或至少一个另外的物理量的基极。电路装置还包括中央路由单元，其连接到多个模块中的若干个。通过中央路由单元，模块可以基于时基和/或基于至少一个其他物理量周期性地交换数据。多个模块被配置为独立于和并行地处理数个模块的其他模块的数据。

6. 发明申请

US20130073256A1 TIMER MODULE AND METHOD FOR TESTING OUTPUT SIGNALS OF A TIMER MODULE 有权
标题翻译：定时器模块和测试定时器模块输出信号的方法
公开(公告)号：US20130073256A1
公开(公告)日：2013-03-21
申请号：US13637130
申请日：2011-03-17
申请人： Eberhard Boehl , Stephen Schmitt , Juergen Hanisch
发明人： Eberhard Boehl , Stephen Schmitt , Juergen Hanisch
IPC分类号： G04F10/00 , G06F15/00
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/1608 , G06F11/1679
摘要： In a timer module having at least two output channels, the at least two output channels are configurable in such a way that they generate redundant output signals, and the generation of the redundant output signals begins synchronously. In addition, the timer module has provides a comparison of the redundant output signals by an EXOR logic operation and stores a result of the EXOR logic operation in a way that allows the result to be retained for an erroneous comparison until it is reset by an access.
摘要翻译：在具有至少两个输出通道的定时器模块中，所述至少两个输出通道可以以这样的方式配置，使得它们产生冗余输出信号，并且冗余输出信号的产生同步开始。此外，定时器模块通过EXOR逻辑运算提供了冗余输出信号的比较，并且以允许结果被保留以进行错误比较的方式存储EXOR逻辑运算的结果，直到其被访问重置为止。

7. 发明申请

US20130076397A1 METHOD AND CIRCUIT CONFIGURATION FOR DETERMINING POSITION MINUS TIME 有权
标题翻译：用于确定下降时间的方法和电路配置
公开(公告)号：US20130076397A1
公开(公告)日：2013-03-28
申请号：US13637113
申请日：2011-03-16
申请人： Eberhard Boehl , Andreas Hempel , Dieter Thoss , Ruben Bartholomae , Stephen Schmitt , Andreas Merker
发明人： Eberhard Boehl , Andreas Hempel , Dieter Thoss , Ruben Bartholomae , Stephen Schmitt , Andreas Merker
IPC分类号： H03K99/00
CPC分类号： H03K99/00 , F02B3/12 , F02B77/087 , F02D41/009 , F02D41/0097 , F02D41/401 , G05B13/026 , G05B2219/2623
摘要： A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.
摘要翻译：提供了一种用于预测待执行的至少一个操作的坐标的数据处理系统的电路配置，所述预测连接到至少一个输入信号，并且是预定义的第一时间值和至少一个预定义的第一时间值的函数代表另一物理变量的值。在所述至少一个输入信号的每次改变时，根据第一值在每种情况下计算第二时间值，并且从第二时间值减去第一时间值以形成第三时间值，和/或计算并且从第二值减去第一值以形成第三值，以便从第三时间值和/或第三值确定至少一个操作的状态为要进行

8. 发明授权

US09602109B2 Method and circuit configuration for determining position minus time 有权
公开(公告)号：US09602109B2
公开(公告)日：2017-03-21
申请号：US13637113
申请日：2011-03-16
申请人： Eberhard Boehl , Andreas Hempel , Dieter Thoss , Ruben Bartholomae , Stephen Schmitt , Andreas Merker
发明人： Eberhard Boehl , Andreas Hempel , Dieter Thoss , Ruben Bartholomae , Stephen Schmitt , Andreas Merker
IPC分类号： H03K99/00 , F02D41/00 , G05B13/02 , F02B3/12 , F02B77/08 , F02D41/40
CPC分类号： H03K99/00 , F02B3/12 , F02B77/087 , F02D41/009 , F02D41/0097 , F02D41/401 , G05B13/026 , G05B2219/2623
摘要： A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.

9. 发明授权

US09184679B2 Method for predicting the duration of a future time interval 有权
标题翻译：预测未来时间间隔持续时间的方法
公开(公告)号：US09184679B2
公开(公告)日：2015-11-10
申请号：US13577475
申请日：2011-01-12
申请人： Eberhard Boehl , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Bernd Becker , Bernard Pawlok
IPC分类号： G06F7/00 , H02P6/00 , F02D41/00
CPC分类号： H02P6/34 , F02D41/009 , F02D41/0097
摘要： A method for predicting a value for a length of a future time interval in which a physical variable changes is described, in which at least one measured value for the length of a past time interval and an instantaneously measured value for a length of an instantaneous time interval are taken into account, m values for lengths of past time intervals being added. A first value precedes the instantaneously measured value by k−1, and an mth value precedes the instantaneously measured value by k−m. The m added values are divided by a value for a length of a past time interval which precedes the instantaneously measured value by k. A ratio of the mentioned values is formed. For determining the value to be predicted, an average error is initially added to the instantaneously measured value, forming a sum. The formed ratio is subsequently applied to this sum.
摘要翻译：描述用于预测物理变量改变的未来时间间隔的长度的值的方法，其中对于过去时间间隔的长度的至少一个测量值和瞬时时间的长度的瞬时测量值考虑间隔时间，添加过去时间间隔的长度的m值。第一个值先于瞬时测量值k-1，第m个值先于瞬时测量值k-m。将m个附加值除以在瞬时测量值之前的过去时间间隔的长度的值。形成上述值的比例。为了确定要预测的值，首先将平均误差加到瞬时测量值上，形成一个和。形成的比率随后应用于这个总和。

10. 发明申请

US20130096872A1 CIRCUIT ARRANGEMENT AND METHOD FOR EVALUATING SIGNALS OF A CRANKSHAFT SENSOR AND OF A CAMSHAFT SENSOR OF AN INTERNAL COMBUSTION ENGINE 有权
标题翻译：用于评估起重机传感器和内燃机的CAMSHAFT传感器的信号的电路布置和方法
公开(公告)号：US20130096872A1
公开(公告)日：2013-04-18
申请号：US13637170
申请日：2011-03-31
申请人： Eberhard Boehl
发明人： Eberhard Boehl
IPC分类号： G06F17/18
CPC分类号： G06F17/18 , F02D41/009 , F02D41/222 , Y02T10/40
摘要： A circuit assemblage and a method for evaluating signals of a crankshaft sensor and of a camshaft sensor of an internal combustion engine are provided, the times at which the signals occur being evaluated. A position signal of a shaft of the internal combustion engine is formed from the times. Storage units are provided which simultaneously store the occurrence times of the signals of the crankshaft sensor and the occurrence times of signals of the camshaft sensor. A decision unit is provided as to whether the position signal is formed from the occurrence times of the signals of the crankshaft sensor or from the occurrence times of the signals of the camshaft sensor.
摘要翻译：提供了用于评估曲轴传感器和内燃机的凸轮轴传感器的信号的电路组合和方法，评估发生信号的时间。内燃机的轴的位置信号由时间形成。提供存储单元，其同时存储曲轴传感器的信号的发生时间和凸轮轴传感器的信号的发生时间。根据曲轴传感器的信号的发生时间或凸轮轴传感器的信号的出现次数，提供位置信号是否形成决定单元。

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