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1. 发明授权

US10541231B2 Semiconductor device having stacked chips 有权
公开(公告)号：US10541231B2
公开(公告)日：2020-01-21
申请号：US16184993
申请日：2018-11-08
申请人： TOSHIBA MEMORY CORPORATION
发明人： Masaru Koyanagi
IPC分类号： H01L25/065 , H03K99/00 , G11C5/06 , G11C8/12 , H01L23/00 , G11C29/00 , G06F3/06 , G11C16/08 , H01L23/48 , H01L23/50 , G11C16/04
摘要： A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

2. 发明申请

US20180076180A1 SEMICONDUCTOR DEVICE HAVING STACKED CHIPS 审中-公开
公开(公告)号：US20180076180A1
公开(公告)日：2018-03-15
申请号：US15819468
申请日：2017-11-21
申请人： TOSHIBA MEMORY CORPORATION
发明人： Masaru KOYANAGI
IPC分类号： H01L25/065 , H03K99/00
CPC分类号： H01L25/0657 , G06F3/0688 , G11C5/063 , G11C8/12 , G11C16/0483 , G11C16/08 , G11C29/88 , H01L23/481 , H01L23/50 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/0401 , H01L2224/04042 , H01L2224/05552 , H01L2224/0557 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/13091 , H01L2924/1438 , H03K99/00 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device includes a first chip having a first via and a second via through the first chip; and a second chip provided on the first chip and having a third via and a fourth via through the second chip. The first chip includes: a first logical operation circuit configured to perform a first logical operation (NOT) on a first address input signal to output a first address output signal to the second chip through the first via; a second logical operation circuit connected to the first logical operation circuit, the second logical operation circuit being configured to perform a second logical operation (XOR) on a second address input signal and the first address output signal to output a second address output signal to the second chip through the second via; and a first activation circuit connected to the second logical operation circuit, the first activation circuit being configured to activate the first chip based on at least the second address output signal.

3. 发明申请

US20130099826A1 POWER DETECTOR 有权
标题翻译：电源检测器
公开(公告)号：US20130099826A1
公开(公告)日：2013-04-25
申请号：US13708501
申请日：2012-12-07
申请人： PANASONIC CORPORATION , Ikuo Terauchi
发明人： Kazuhiro KONDO , Katsuhiko TANAKA
IPC分类号： H03K99/00
CPC分类号： H03K99/00 , H03K17/145 , H03K17/223
摘要： In a power detector, a comparator for detection receives an input signal and a reference voltage, and compares the input signal to the reference voltage around the switching time of active and inactive states of the output of the comparator in accordance with an output of an input switching signal generator. Except for the switching time, an input voltage for non-use of the comparator is inputs to the comparator for detection, and the differential inputs are fixed to the same potential. Therefore, aging reduction in the accuracy of power detection caused by BT degradation is effectively mitigated.
摘要翻译：在功率检测器中，用于检测的比较器接收输入信号和参考电压，并且根据输入的输出将输入信号与比较器的输出的有效和无效状态的切换时间周围的参考电压进行比较开关信号发生器。除了开关时间外，不使用比较器的输入电压是比较器的输入，用于检测，差分输入固定为相同的电位。因此，BT降解引起的功率检测精度的老化降低得到有效的缓解。

4. 发明授权

US10985141B2 Semiconductor device having stacked chips 有权
公开(公告)号：US10985141B2
公开(公告)日：2021-04-20
申请号：US16726752
申请日：2019-12-24
申请人： TOSHIBA MEMORY CORPORATION
发明人： Masaru Koyanagi
IPC分类号： H01L25/065 , H03K99/00 , G11C5/06 , G11C8/12 , H01L23/00 , G11C29/00 , G06F3/06 , G11C16/08 , H01L23/48 , H01L23/50 , G11C16/04
摘要： A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

5. 发明授权

US10157894B2 Semiconductor device having stacked chips 有权
公开(公告)号：US10157894B2
公开(公告)日：2018-12-18
申请号：US15819468
申请日：2017-11-21
申请人： TOSHIBA MEMORY CORPORATION
发明人： Masaru Koyanagi
IPC分类号： H01L25/07 , H01L25/065 , H03K99/00 , G06F3/06 , G11C5/06 , G11C8/12 , G11C29/00 , G11C16/08 , H01L23/48 , H01L23/50 , G11C16/04 , H01L23/00
摘要： A semiconductor device includes a first chip having a first via and a second via through the first chip; and a second chip provided on the first chip and having a third via and a fourth via through the second chip. The first chip includes: a first logical operation circuit configured to perform a first logical operation (NOT) on a first address input signal to output a first address output signal to the second chip through the first via; a second logical operation circuit connected to the first logical operation circuit, the second logical operation circuit being configured to perform a second logical operation (XOR) on a second address input signal and the first address output signal to output a second address output signal to the second chip through the second via; and a first activation circuit connected to the second logical operation circuit, the first activation circuit being configured to activate the first chip based on at least the second address output signal.

6. 发明授权

US09853013B2 Semiconductor device having stacked chips 有权
公开(公告)号：US09853013B2
公开(公告)日：2017-12-26
申请号：US15232391
申请日：2016-08-09
申请人： TOSHIBA MEMORY CORPORATION
发明人： Masaru Koyanagi
IPC分类号： H01L25/065 , H03K99/00 , G06F3/06 , G11C5/06 , G11C8/12 , G11C29/00 , G11C16/08 , H01L23/48 , H01L23/50 , G11C16/04 , H01L23/00
CPC分类号： H01L25/0657 , G06F3/0688 , G11C5/063 , G11C8/12 , G11C16/0483 , G11C16/08 , G11C29/88 , H01L23/481 , H01L23/50 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/0401 , H01L2224/04042 , H01L2224/05552 , H01L2224/0557 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/13091 , H01L2924/1438 , H03K99/00 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, wherein these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, and includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.

7. 发明授权

US09602109B2 Method and circuit configuration for determining position minus time 有权
公开(公告)号：US09602109B2
公开(公告)日：2017-03-21
申请号：US13637113
申请日：2011-03-16
申请人： Eberhard Boehl , Andreas Hempel , Dieter Thoss , Ruben Bartholomae , Stephen Schmitt , Andreas Merker
发明人： Eberhard Boehl , Andreas Hempel , Dieter Thoss , Ruben Bartholomae , Stephen Schmitt , Andreas Merker
IPC分类号： H03K99/00 , F02D41/00 , G05B13/02 , F02B3/12 , F02B77/08 , F02D41/40
CPC分类号： H03K99/00 , F02B3/12 , F02B77/087 , F02D41/009 , F02D41/0097 , F02D41/401 , G05B13/026 , G05B2219/2623
摘要： A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.

8. 发明申请

US20210210467A1 SEMICONDUCTOR DEVICE HAVING STACKED CHIPS 有权
公开(公告)号：US20210210467A1
公开(公告)日：2021-07-08
申请号：US17206395
申请日：2021-03-19
申请人： TOSHIBA MEMORY CORPORATION
发明人： Masaru KOYANAGI
IPC分类号： H01L25/065 , H03K99/00 , G11C5/06 , G11C8/12 , H01L23/00 , G11C29/00 , G06F3/06 , G11C16/08 , H01L23/48 , H01L23/50
摘要： A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

9. 发明授权

US10784764B2 Switched-mode DC/DC converter having a bootstrapped high-side driver 有权
公开(公告)号：US10784764B2
公开(公告)日：2020-09-22
申请号：US16265478
申请日：2019-02-01
申请人： Texas Instruments Incorporated
发明人： Eduardas Jodka , Julian Becker , Carsten Stoerk
IPC分类号： H03K99/00 , H02M1/08 , H02M3/155 , H03K17/687 , H02M1/00
摘要： A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

10. 发明申请

US20140062587A1 SEMICONDUCTOR DEVICE HAVING STACKED CHIPS 有权
标题翻译：具有堆叠晶圆的半导体器件
公开(公告)号：US20140062587A1
公开(公告)日：2014-03-06
申请号：US13843165
申请日：2013-03-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masaru KOYANAGI
IPC分类号： H03K99/00
CPC分类号： H01L25/0657 , G06F3/0688 , G11C5/063 , G11C8/12 , G11C16/0483 , G11C16/08 , G11C29/88 , H01L23/481 , H01L23/50 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/0401 , H01L2224/04042 , H01L2224/05552 , H01L2224/0557 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/13091 , H01L2924/1438 , H03K99/00 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.
摘要翻译：根据一个实施例，半导体器件包括芯片和第一选择电路。每个芯片至少具有用于发送至少第一和第二地址信号的第一和第二通孔，这些芯片被堆叠以经由第一和第二通孔电连接。第一选择电路设置在每个芯片中，包括至少基于第一和第二地址信号选择芯片的逻辑电路，并将第一和第二地址信号的操作结果提供给后续的芯片。

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