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1. 发明申请

US20090037617A1 MIDDLE MANAGEMENT OF INPUT/OUTPUT IN SERVER SYSTEMS 审中-公开
标题翻译：服务器系统中输入/输出的中间管理
公开(公告)号：US20090037617A1
公开(公告)日：2009-02-05
申请号：US11932265
申请日：2007-10-31
申请人： Dwight D. RILEY , James Xuan Dinh , Barry S. Basile , Kenneth A. Jansen , Hubert E. Brinkmann , David L. Matthews , Paul V. Brownell
发明人： Dwight D. RILEY , James Xuan Dinh , Barry S. Basile , Kenneth A. Jansen , Hubert E. Brinkmann , David L. Matthews , Paul V. Brownell
IPC分类号： G06F13/10 , G06F13/14
CPC分类号： G06F13/387
摘要： A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.
摘要翻译：提供中间管理器和方法以使得多个主机设备能够共享一个或多个输入/输出设备。中间管理器初始化每个共享输入/输出设备，并将每个输入/输出设备的一个或多个功能绑定到系统中的特定主机节点，使得主机只能访问它们所绑定的功能。中间管理器还可以使用配置寄存器映射来将实际配置寄存器中的值转换为多个主机设备中的每一个的唯一修改值，使得每个主机设备可访问和使用共享输入/输出设备，而不管固件如何或在其上操作的操作系统。

2. 发明申请

US20090037609A1 MIDDLE MANAGEMENT OF INPUT/OUTPUT IN SERVER SYSTEMS 审中-公开
公开(公告)号：US20090037609A1
公开(公告)日：2009-02-05
申请号：US11830747
申请日：2007-07-30
申请人： Dwight D. Riley , James X. Dinh , Barry S. Basile , Kenneth A. Jansen , Hubert E. Brinkmann , David L. Matthews , Paul V. Brownell
发明人： Dwight D. Riley , James X. Dinh , Barry S. Basile , Kenneth A. Jansen , Hubert E. Brinkmann , David L. Matthews , Paul V. Brownell
IPC分类号： G06F3/00
CPC分类号： G06F3/0227
摘要： A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

3. 发明授权

US6119228A Method for securely communicating remote control commands in a computer network 失效
标题翻译：在计算机网络中安全地通信远程控制命令的方法
公开(公告)号：US6119228A
公开(公告)日：2000-09-12
申请号：US916273
申请日：1997-08-22
申请人： Michael F. Angelo , David L. Collins , Donald D. Kim , Kenneth A. Jansen
发明人： Michael F. Angelo , David L. Collins , Donald D. Kim , Kenneth A. Jansen
IPC分类号： G06F1/26 , G06F13/00 , G06F15/00 , G09C1/00 , H04L12/24 , H04L29/06 , H02J13/00
CPC分类号： H04L41/28 , H04L63/0442 , H04L63/065 , H04L63/123
摘要： A method for providing secure remote control commands in a distributing computer environment. In the preferred embodiment of the invention, a network administrator or network management software creates a shutdown record, including an index or time stamp, for powering down a specified network computer(s). Prior to broadcast over the network, a secure one-way hash function is performed on the shutdown record. The result of the one-way hash function is encrypted using the network administrator's private key, thereby generating a digital signature that can be verified by specially configured network nodes. The digital signature is appended to the original shutdown record prior to broadcast to the network. Upon receiving the broadcast message, the targeted network computer(s) validates the broadcast message by verifying the digital signature of the packet or frame. The validation process is performed by decrypting the hash value representation of the shutdown record using the network administrator's public key. A one-way hash function is also performed on the original shutdown record portion of the received message. If the two values match, the broadcast message is determined to be authentic and the shutdown control code is executed. The invention insures that the shutdown command was neither modified in transit nor originated from an unauthorized source.
摘要翻译：一种用于在分发计算机环境中提供安全远程控制命令的方法。在本发明的优选实施例中，网络管理员或网络管理软件创建关闭记录，包括用于断电指定的网络计算机的索引或时间戳。在通过网络广播之前，对关闭记录执行安全的单向散列函数。使用网络管理员的私钥对单向散列函数的结果进行加密，从而生成可由特殊配置的网络节点进行验证的数字签名。数字签名在广播到网络之前附加到原始关闭记录。在接收到广播消息时，目标网络计算机通过验证分组或帧的数字签名来验证广播消息。验证过程通过使用网络管理员的公钥解密关闭记录的散列值表示来执行。还对接收到的消息的原始关闭记录部分执行单向散列函数。如果两个值相匹配，则确定广播消息是可信的，并且执行关闭控制代码。本发明确保了关闭命令在传输过程中既未被修改也不是源自未经授权的源。

4. 发明授权

US5737604A Method and apparatus for independently resetting processors and cache controllers in multiple processor systems 失效
公开(公告)号：US5737604A
公开(公告)日：1998-04-07
申请号：US723841
申请日：1996-09-30
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F12/08 , G06F15/177 , G06F9/00
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.

5. 发明授权

US5465360A Method and apparatus for independently resetting processors and cache controllers in multiple processor systems 失效
标题翻译：用于在多个处理器系统中独立地重置处理器和高速缓存控制器的方法和装置
公开(公告)号：US5465360A
公开(公告)日：1995-11-07
申请号：US152241
申请日：1993-11-12
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F12/08 , G06F15/177 , G06F9/00
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
摘要翻译：一种用于在多处理器，高速缓冲存储器系统中的程序控制下分别独立地重置主处理器20和第二处理器120的方法和系统。复位处理器20和120而不使高速缓冲存储器控制器24和124复位。

6. 发明授权

US06463529B1 Processor based system with system wide reset and partial system reset capabilities 失效
标题翻译：基于处理器的系统具有系统复位和部分系统复位功能
公开(公告)号：US06463529B1
公开(公告)日：2002-10-08
申请号：US08797036
申请日：1997-02-10
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley
IPC分类号： G06F124
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The processing unit is reset in response to a system reset signal being asserted at a reset input node and only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at a partial-reset input node. The system can also include a number of other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.
摘要翻译：基于处理器的系统包括处理单元。处理单元至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。处理单元响应于在复位输入节点断言的系统复位信号被复位，并且响应于部分复位输入节点断言的部分复位信号仅复位处理单元的选定部分。该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

7. 发明授权

US06370657B1 Hot processor swap in a multiprocessor personal computer system 有权
标题翻译：多处理器个人计算机系统中的热处理器交换
公开(公告)号：US06370657B1
公开(公告)日：2002-04-09
申请号：US09196264
申请日：1998-11-19
申请人： Kenneth A. Jansen , Sompong P. Olarig , John E. Jenne
发明人： Kenneth A. Jansen , Sompong P. Olarig , John E. Jenne
IPC分类号： G06F1100
CPC分类号： G06F11/0793 , G06F11/0724 , G06F13/4081
摘要： A scheme may be used to remove or replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, the bus to which the processor is coupled is identified so that all processors coupled to the bus may be placed in sleep mode. This act does not alter the normal operation of processors that may be coupled to another bus. Once the processors are in sleep mode, the processor may be removed or replaced. Afterward, all processors may be returned to normal operation.
摘要翻译：可以使用方案来移除或替换多处理器计算机中的处理器，而不需要关闭计算机来替换处理器。在该方案中，识别处理器耦合到的总线，使得耦合到总线的所有处理器可以被置于睡眠模式。该动作不会改变可能耦合到另一总线的处理器的正常操作。一旦处理器处于睡眠模式，处理器可能会被删除或更换。之后，所有处理器都可以恢复正常运行。

8. 发明授权

US06314515B1 Resetting multiple processors in a computer system 失效
标题翻译：在计算机系统中重置多个处理器
公开(公告)号：US06314515B1
公开(公告)日：2001-11-06
申请号：US09356472
申请日：1999-07-19
申请人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
发明人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
IPC分类号： G06F15177
CPC分类号： G06F11/1417 , G06F9/4403 , G06F9/4405 , G06F9/4416 , G06F11/2038 , G06F11/2043 , G06F11/22 , G06F11/2284 , G06F15/177
摘要： Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
摘要翻译：公开了允许使用单个ROM启动多个处理器的两种设计变型。在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。第一种技术适用于一般的多处理器系统，因为这种设计的实现可以从外部软件运行，也可以从添加到正在使用它的特定机器的操作系统运行。第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

9. 发明授权

US5497497A Method and apparatus for resetting multiple processors using a common ROM 失效
标题翻译：使用公共ROM复位多个处理器的方法和装置
公开(公告)号：US5497497A
公开(公告)日：1996-03-05
申请号：US51601
申请日：1993-04-22
申请人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
发明人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
IPC分类号： G06F9/445 , G06F11/14 , G06F11/20 , G06F11/22 , G06F9/40 , G06F9/42 , G06F11/34
CPC分类号： G06F11/1417 , G06F11/22 , G06F11/2284 , G06F15/177 , G06F9/4403 , G06F9/4405 , G06F11/2038 , G06F11/2043 , G06F9/4416
摘要： Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
摘要翻译：两种设计变化，允许多个处理器使用单个ROM启动。在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。第一种技术适用于一般的多处理器系统，因为这种设计的实现可以从外部软件运行，也可以从添加到正在使用它的特定机器的操作系统运行。第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

10. 发明授权

US6032257A Hardware theft-protection architecture 失效
标题翻译：硬件防盗架构
公开(公告)号：US6032257A
公开(公告)日：2000-02-29
申请号：US927114
申请日：1997-08-29
申请人： Sompong P. Olarig , Michael F. Angelo , Kenneth A. Jansen
发明人： Sompong P. Olarig , Michael F. Angelo , Kenneth A. Jansen
IPC分类号： G06F21/00 , G08B13/14 , G06F13/00 , H04L9/00
CPC分类号： G08B13/1418 , G06F21/31 , G06F21/575 , G06F21/88 , G06F2207/7219 , G06F2211/1097 , G06F2221/2103 , G06F2221/2129
摘要： A method of theft protection for computers and computer related hardware. Warranty fraud, theft of proprietary technology, and hardware theft are minimized by encoding the hardware components such that a digitally authenticated handshake must be performed between the system and the component at power-up. If the handshake is successful, normal operation continues with all enhancements. If the handshake is unsuccessful, the device is disabled or shifted into a lower performance mode.
摘要翻译：一种计算机和计算机相关硬件的防盗方法。通过对硬件组件进行编码，可以最大限度地减少保修欺诈，盗用专有技术和硬件盗窃，从而必须在上电时在系统和组件之间进行数字认证的握手。如果握手成功，正常操作将继续进行所有增强功能。如果握手失败，则设备被禁用或转移到较低的性能模式。

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