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1. 发明授权

US5737604A Method and apparatus for independently resetting processors and cache controllers in multiple processor systems 失效
公开(公告)号：US5737604A
公开(公告)日：1998-04-07
申请号：US723841
申请日：1996-09-30
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F12/08 , G06F15/177 , G06F9/00
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.

2. 发明授权

US5465360A Method and apparatus for independently resetting processors and cache controllers in multiple processor systems 失效
标题翻译：用于在多个处理器系统中独立地重置处理器和高速缓存控制器的方法和装置
公开(公告)号：US5465360A
公开(公告)日：1995-11-07
申请号：US152241
申请日：1993-11-12
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F12/08 , G06F15/177 , G06F9/00
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
摘要翻译：一种用于在多处理器，高速缓冲存储器系统中的程序控制下分别独立地重置主处理器20和第二处理器120的方法和系统。复位处理器20和120而不使高速缓冲存储器控制器24和124复位。

3. 发明授权

US5611078A Method and apparatus for independently resetting processors and cache controllers in multiple processor systems 失效
标题翻译：用于在多个处理器系统中独立地重置处理器和缓存控制器的方法和装置
公开(公告)号：US5611078A
公开(公告)日：1997-03-11
申请号：US480874
申请日：1995-06-07
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F12/08 , G06F15/177 , G06F13/00
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
摘要翻译：一种用于在多处理器，高速缓冲存储器系统中的程序控制下分别独立地重置主处理器20和第二处理器120的方法和系统。复位处理器20和120而不使高速缓冲存储器控制器24和124复位。

4. 发明授权

US5870602A Multi-processor system with system wide reset and partial system reset capabilities 失效
标题翻译：具有系统复位和部分系统复位功能的多处理器系统
公开(公告)号：US5870602A
公开(公告)日：1999-02-09
申请号：US14369
申请日：1998-01-27
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F9/00
CPC分类号： G06F1/24
摘要： A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.
摘要翻译：多处理器系统包括第一和第二处理单元。这些处理单元中的每一个至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。每个处理单元响应于系统复位信号被复位，但只响应于部分复位信号来复位处理单元的选定部分。该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

5. 发明授权

US06463529B1 Processor based system with system wide reset and partial system reset capabilities 失效
标题翻译：基于处理器的系统具有系统复位和部分系统复位功能
公开(公告)号：US06463529B1
公开(公告)日：2002-10-08
申请号：US08797036
申请日：1997-02-10
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley
IPC分类号： G06F124
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The processing unit is reset in response to a system reset signal being asserted at a reset input node and only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at a partial-reset input node. The system can also include a number of other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.
摘要翻译：基于处理器的系统包括处理单元。处理单元至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。处理单元响应于在复位输入节点断言的系统复位信号被复位，并且响应于部分复位输入节点断言的部分复位信号仅复位处理单元的选定部分。该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

6. 发明授权

US5392436A Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration 失效
标题翻译：在单个处理器中具有较低优先级多处理器仲裁和较高优先级的两级系统总线仲裁以及多个总线主机仲裁
公开(公告)号：US5392436A
公开(公告)日：1995-02-21
申请号：US249665
申请日：1994-05-26
申请人： Kenneth A. Jansen , Montgomery C. McGraw , David A. Miller , Paul R. Culley
发明人： Kenneth A. Jansen , Montgomery C. McGraw , David A. Miller , Paul R. Culley
IPC分类号： G06F13/362 , G06F13/36 , G06F13/18
CPC分类号： G06F13/362
摘要： A method and apparatus for arbitrating between multiple processors that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme. When control of the bus is allocated to the single processor, the multiprocessor arbitration arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.
摘要翻译：一种用于在可被并入设计成仅包括单个处理器的仲裁方案中的多个处理器之间进行仲裁的方法和装置。该方法包括将每个处理器的各个总线请求整合到提供给单处理器仲裁方案的单个总线请求中。当总线的控制被分配给单个处理器时，多处理器仲裁在请求总线的处理器之间进行仲裁。所使用的总线协议包括最近最少使用的用于授予对多个处理器的总线访问的方法，该方法与用于给予一个处理器优先级的方式相比，用于访问总线。该协议还包括在预设时间段内控制总线的各个处理器的中断保护。

7. 发明授权

US06314515B1 Resetting multiple processors in a computer system 失效
标题翻译：在计算机系统中重置多个处理器
公开(公告)号：US06314515B1
公开(公告)日：2001-11-06
申请号：US09356472
申请日：1999-07-19
申请人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
发明人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
IPC分类号： G06F15177
CPC分类号： G06F11/1417 , G06F9/4403 , G06F9/4405 , G06F9/4416 , G06F11/2038 , G06F11/2043 , G06F11/22 , G06F11/2284 , G06F15/177
摘要： Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
摘要翻译：公开了允许使用单个ROM启动多个处理器的两种设计变型。在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。第一种技术适用于一般的多处理器系统，因为这种设计的实现可以从外部软件运行，也可以从添加到正在使用它的特定机器的操作系统运行。第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

8. 发明授权

US5497497A Method and apparatus for resetting multiple processors using a common ROM 失效
标题翻译：使用公共ROM复位多个处理器的方法和装置
公开(公告)号：US5497497A
公开(公告)日：1996-03-05
申请号：US51601
申请日：1993-04-22
申请人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
发明人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
IPC分类号： G06F9/445 , G06F11/14 , G06F11/20 , G06F11/22 , G06F9/40 , G06F9/42 , G06F11/34
CPC分类号： G06F11/1417 , G06F11/22 , G06F11/2284 , G06F15/177 , G06F9/4403 , G06F9/4405 , G06F11/2038 , G06F11/2043 , G06F9/4416
摘要： Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
摘要翻译：两种设计变化，允许多个处理器使用单个ROM启动。在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。第一种技术适用于一般的多处理器系统，因为这种设计的实现可以从外部软件运行，也可以从添加到正在使用它的特定机器的操作系统运行。第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

9. 发明授权

US5867703A Common reset ROM 失效
标题翻译：普通复位ROM
公开(公告)号：US5867703A
公开(公告)日：1999-02-02
申请号：US14154
申请日：1998-01-27
申请人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
发明人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
IPC分类号： G06F9/445 , G06F11/14 , G06F11/20 , G06F11/22 , G06F9/06
CPC分类号： G06F11/1417 , G06F11/22 , G06F11/2284 , G06F15/177 , G06F9/4403 , G06F9/4405 , G06F11/2038 , G06F11/2043 , G06F9/4416
摘要： Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
摘要翻译：公开了允许使用单个ROM启动多个处理器的两种设计变型。在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。第一种技术适用于一般的多处理器系统，因为这种设计的实现可以从外部软件运行，也可以从添加到正在使用它的特定机器的操作系统运行。第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

10. 发明授权

US5729675A Apparatus for initializing a multiple processor computer system using a common ROM 失效
标题翻译：用于使用公共ROM初始化多处理器计算机系统的装置
公开(公告)号：US5729675A
公开(公告)日：1998-03-17
申请号：US700300
申请日：1996-08-20
申请人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
发明人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
IPC分类号： G06F9/445 , G06F11/14 , G06F11/20 , G06F11/22 , G06F1/24 , G06F9/24
CPC分类号： G06F11/1417 , G06F11/22 , G06F11/2284 , G06F15/177 , G06F9/4403 , G06F9/4405 , G06F11/2038 , G06F11/2043 , G06F9/4416
摘要： Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
摘要翻译：公开了允许使用单个ROM启动多个处理器的两种设计变型。在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。第一种技术适用于一般的多处理器系统，因为该设计的实现可以从外部软件或从使用它的特定机器的操作系统的添加运行。第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

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