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1. 发明申请

US20060145274A1 NFETs using gate induced stress modulation 审中-公开
公开(公告)号：US20060145274A1
公开(公告)日：2006-07-06
申请号：US11365502
申请日：2006-03-02
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L29/94
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828
摘要： A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.

2. 发明申请

US20060124993A1 SIDEWALL SEMICONDUCTOR TRANSISTORS 有权
标题翻译：端子半导体晶体管
公开(公告)号：US20060124993A1
公开(公告)日：2006-06-15
申请号：US10905041
申请日：2004-12-13
申请人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/1083 , H01L29/66795
摘要： A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.
摘要翻译：一种新颖的晶体管结构及其制造方法。晶体管结构包括（a）衬底和（b）衬底上的半导体区域，栅极介电区域和栅极区域，其中栅极电介质区域夹在半导体区域和栅极区域之间，其中半导体区域通过所述栅极电介质区域与所述栅极区域电绝缘，其中所述半导体区域包括沟道区域和第一和第二源极/漏极区域，其中所述沟道区域夹在所述第一和第二源极/漏极区域之间，其中所述第一和/ 第二源极/漏极区域与栅极区域对准，其中沟道区域和栅极电介质区域（i）共享基本上垂直于衬底顶表面的界面，以及（ii）不共享任何界面表面其基本上平行于衬底的顶表面。

3. 发明申请

US20050269561A1 Strained Si on multiple materials for bulk or SOI substrates 有权
标题翻译：应变Si在多种材料上用于体或SOI衬底
公开(公告)号：US20050269561A1
公开(公告)日：2005-12-08
申请号：US10859736
申请日：2004-06-03
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov , Huilong Zhu
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov , Huilong Zhu
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/78 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层。

4. 发明申请

US20050148133A1 Method of making strained channel CMOS transistors having lattice-mismatched epitaxial 有权
标题翻译：制造具有晶格失配外延的应变通道CMOS晶体管的方法
公开(公告)号：US20050148133A1
公开(公告)日：2005-07-07
申请号：US11052675
申请日：2005-02-07
申请人： Huaje Chen , Dureseti Chidambarrao , Omer Dokumaci , Haining Yang
发明人： Huaje Chen , Dureseti Chidambarrao , Omer Dokumaci , Haining Yang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/00
CPC分类号： H01L29/6653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7848
摘要： A method is provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a first single-crystal semiconductor region having a first composition. A stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a single-crystal semiconductor layer having a second composition such that the single-crystal semiconductor layer is lattice-mismatched to the first region. The semiconductor layer is formed over the source and drain regions and optionally over the extension regions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or the semiconductor layer having the second composition is not formed at all in the NFET.
摘要翻译：提供一种方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在具有第一组成的第一单晶半导体区域中的沟道区。应力以第一幅度施加到PFET的沟道区，但不以该尺寸施加到NFET的沟道区。应力由具有第二组成的单晶半导体层施加使得单晶半导体层与第一区域晶格失配。半导体层形成在源极和漏极区域上，并且任选地在距离PFET的沟道区第一距离处的PFET的延伸区域上方形成，并且形成在NFET的源极和漏极区域之上，距离 NFET的沟道区域或具有第二组成的半导体层完全不形成在NFET中。

5. 发明申请

US20050139930A1 Strained dislocation-free channels for CMOS and method of manufacture 有权
标题翻译：用于CMOS的应变无位错通道和制造方法
公开(公告)号：US20050139930A1
公开(公告)日：2005-06-30
申请号：US11061445
申请日：2005-02-22
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L20060101 , H01L21/00 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/04 , H01L31/036 , H01R4/64
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/66621 , Y10S438/933
摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.
摘要翻译：半导体器件及半导体器件的制造方法。半导体器件包括用于pFET和nFET的沟道。在nFET沟道的沟道中生长SiGe层，并且在pFET沟道中生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配，以在覆盖的生长的外延层中产生应力分量。在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。在另一实施方案中，SiGe层在nFET和pFET沟道中生长。在这种实现中，pFET通道中的应力水平应该大于3GPa。

6. 发明申请

US20050064686A1 STRAINED SILICON ON RELAXED SIGE FILM WITH UNIFORM MISFIT DISLOCATION DENSITY 有权
标题翻译：松散信号膜上的应变硅，具有均匀杂散偏差密度
公开(公告)号：US20050064686A1
公开(公告)日：2005-03-24
申请号：US10667603
申请日：2003-09-23
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/205 , C30B1/00 , H01L21/20 , H01L21/265 , H01L21/322 , H01L21/324 , H01L21/36 , H01L29/10
CPC分类号： H01L21/26506 , H01L21/324 , H01L29/1054
摘要： A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.
摘要翻译：提供一种形成半导体衬底结构的方法。在硅衬底上形成压缩应变SiGe层。原子被离子注入SiGe层以造成范围内的损伤。进行退火以松弛应变的SiGe层。在退火过程中，间隙位错环形成均匀分布在SiGe层中。间隙位错环为SiGe层和硅衬底之间的失配位错的成核提供了基础。由于间隙位错环分布均匀，因此错位位置也均匀分布，从而松弛SiGe层。在松弛的SiGe层上形成拉伸应变硅层。

7. 发明申请

US20050064646A1 NFETs using gate induced stress modulation 失效
标题翻译：使用栅极诱导应力调制的NFET
公开(公告)号：US20050064646A1
公开(公告)日：2005-03-24
申请号：US10667601
申请日：2003-09-23
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828
摘要： A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.
摘要翻译：一种用于制造集成电路的方法，该集成电路包括通过用掩模覆盖p型场效应晶体管的多个半导体器件，包括n型场效应晶体管和p型场效应晶体管，并且氧化栅极多晶硅的一部分的n型场效应晶体管，使得在n型场效应晶体管的沟道内形成拉伸机械应力。

8. 发明申请

US20070228472A1 SILICON DEVICE ON SI: C-OI AND SGOI AND METHOD OF MANUFACTURE 有权
公开(公告)号：US20070228472A1
公开(公告)日：2007-10-04
申请号：US11757874
申请日：2007-06-04
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L27/12
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

9. 发明申请

US20070184621A1 MOSFET WTH HIGH ANGLE SIDEWALL GATE AND CONTACTS FOR REDUCED MILLER CAPACITANCE 审中-公开
标题翻译： MOSFET WTH高角度门窗和联系人，以减少铣床电容
公开(公告)号：US20070184621A1
公开(公告)日：2007-08-09
申请号：US11694225
申请日：2007-03-30
申请人： Dureseti Chidambarrao , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Huilong Zhu
发明人： Dureseti Chidambarrao , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7836 , H01L21/26586 , H01L21/28518 , H01L21/76804 , H01L29/1083 , H01L29/665 , H01L29/6659
摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.
摘要翻译：本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面区。与具有直壁栅电极和金属触点的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

10. 发明申请

US20070166897A1 STRAINED Si ON MULTIPLE MATERIALS FOR BULK OR SOI SUBSTRATES 失效
标题翻译：用于大块或SOI衬底的多种材料上的应变Si
公开(公告)号：US20070166897A1
公开(公告)日：2007-07-19
申请号：US11694373
申请日：2007-03-30
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov , Huilong Zhu
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov , Huilong Zhu
IPC分类号： H01L21/84
CPC分类号： H01L29/78 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrates a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含硅部分，衬底的含Si部分顶部的压缩层，以及半导体硅层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层。

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