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1. 发明授权

US08368125B2 Multiple orientation nanowires with gate stack stressors 失效
标题翻译：具有栅堆叠应力的多取向纳米线
公开(公告)号：US08368125B2
公开(公告)日：2013-02-05
申请号：US12505580
申请日：2009-07-20
申请人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
发明人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
IPC分类号： H01L27/085
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/0673 , H01L29/517 , H01L29/518 , H01L29/7842 , H01L29/7845
摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
摘要翻译：电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加取决于通道长度相对于晶体结构的对准。给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

2. 发明授权

US07989233B2 Semiconductor nanowire with built-in stress 失效
公开(公告)号：US07989233B2
公开(公告)日：2011-08-02
申请号：US13004340
申请日：2011-01-11
申请人： Lidija Sekaric , Dureseti Chidambarrao , Xiao H. Liu
发明人： Lidija Sekaric , Dureseti Chidambarrao , Xiao H. Liu
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

3. 发明授权

US08492802B2 Multiple orientation nanowires with gate stack sensors 失效
标题翻译：具有栅极堆叠传感器的多取向纳米线
公开(公告)号：US08492802B2
公开(公告)日：2013-07-23
申请号：US13593659
申请日：2012-08-24
申请人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
发明人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
IPC分类号： H01L27/085
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/0673 , H01L29/517 , H01L29/518 , H01L29/7842 , H01L29/7845
摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
摘要翻译：电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加取决于通道长度相对于晶体结构的对准。给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

4. 发明申请

US20130015507A1 MULTIPLE ORIENTATION NANOWIRES WITH GATE STACK SENSORS 失效
标题翻译：多个定位纳米与门盖传感器
公开(公告)号：US20130015507A1
公开(公告)日：2013-01-17
申请号：US13593659
申请日：2012-08-24
申请人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
发明人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
IPC分类号： H01L27/092
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/0673 , H01L29/517 , H01L29/518 , H01L29/7842 , H01L29/7845
摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
摘要翻译：电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加取决于通道长度相对于晶体结构的对准。给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

5. 发明授权

US08237150B2 Nanowire devices for enhancing mobility through stress engineering 有权
标题翻译：纳米线装置通过应力工程提高移动性
公开(公告)号：US08237150B2
公开(公告)日：2012-08-07
申请号：US12417808
申请日：2009-04-03
申请人： Dureseti Chidambarrao , Xiao H. Liu , Lidija Sekaric
发明人： Dureseti Chidambarrao , Xiao H. Liu , Lidija Sekaric
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/84 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938 , Y10S977/957
摘要： A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors.
摘要翻译：在第一半导体纳米线上形成p型半导体纳米线晶体管，在第二半导体纳米线上形成n型半导体纳米线晶体管。第一和第二半导体纳米线具有具有不同宽度与高度比的矩形横截面面积。选择每个半导体纳米线晶体管的半导体纳米线的类型，使得顶表面和底表面在具有更大宽度与高度比的半导体纳米线中提供比单元宽度更大的导通电流，而侧壁表面提供更大的具有比宽度与高度比较小的另一半导体纳米线中的顶表面和底表面的每单位宽度的电流。可以在第一和第二半导体纳米线晶体管上形成不同类型的应力产生材料层以提供相反类型的应力，其可用于增强第一和第二半导体纳米线晶体管的导通电流。

6. 发明申请

US20110175063A1 SEMICONDUCTOR NANOWIRES HAVING MOBILITY-OPTIMIZED ORIENTATIONS 有权
标题翻译：具有移动优化方位的半导体纳米级
公开(公告)号：US20110175063A1
公开(公告)日：2011-07-21
申请号：US13075551
申请日：2011-03-30
申请人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
发明人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
IPC分类号： H01L29/775
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译：通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分变薄。

7. 发明授权

US07943530B2 Semiconductor nanowires having mobility-optimized orientations 有权
标题翻译：具有移动性优化取向的半导体纳米线
公开(公告)号：US07943530B2
公开(公告)日：2011-05-17
申请号：US12417796
申请日：2009-04-03
申请人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
发明人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译：通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分的稀化。

8. 发明申请

US20100252815A1 STRUCTURALLY STABILIZED SEMICONDUCTOR NANOWIRE 有权
标题翻译：结构稳定的半导体纳米级
公开(公告)号：US20100252815A1
公开(公告)日：2010-10-07
申请号：US12417815
申请日：2009-04-03
申请人： Dureseti Chidambarrao , Lidija Sekaric
发明人： Dureseti Chidambarrao , Lidija Sekaric
IPC分类号： H01L29/78 , H01L21/336 , H01L21/768
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/76838 , H01L29/0673 , H01L29/068 , H01L29/125 , H01L29/42392 , H01L29/78696 , H01L2221/1094
摘要： In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During the thinning process that forms a semiconductor nanowire, the taper at the end portions of the semiconductor nanowire provides enhanced mechanical strength to prevent structural buckling or bending. In another embodiment, a semiconductor nanowire having bulge portions are formed by preventing the thinning of a semiconductor link portion at pre-selected positions. The bulge portions having a greater width than a middle portion of the semiconductor nanowire provides enhanced mechanical strength during thinning of the semiconductor link portion so that structural damage to the semiconductor nanowire is avoided during thinning.
摘要翻译：在一个实施例中，提供了具有从中间部分到相邻半导体焊盘的距离的单调增加的宽度的半导体纳米线。具有锥形端部的半导体连接部分被光刻图案化。在形成半导体纳米线的薄化工艺期间，半导体纳米线端部的锥度提供增强的机械强度以防止结构弯曲或弯曲。在另一个实施例中，通过防止半导体连接部分在预先选定位置的变薄而形成具有凸出部分的半导体纳米线。具有比半导体纳米线的中间部分更大的宽度的凸起部分在半导体连接部分的薄化期间提供增强的机械强度，使得在减薄期间避免对半导体纳米线的结构损坏。

9. 发明申请

US20100252801A1 SEMICONDUCTOR NANOWIRE WITH BUILT-IN STRESS 有权
标题翻译：半导体纳米管与内置应力
公开(公告)号：US20100252801A1
公开(公告)日：2010-10-07
申请号：US12417819
申请日：2009-04-03
申请人： Lidija Sekaric , Dureseti Chidambarrao , Xiao H. Liu
发明人： Lidija Sekaric , Dureseti Chidambarrao , Xiao H. Liu
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
摘要翻译：将两端具有两个半导体焊盘的半导体纳米线悬置在衬底上。在半导体衬底的两个半导体衬底上形成有应力产生衬垫部分，同时露出半导体纳米线的中间部分。在半导体纳米线的中间部分形成栅极电介质和栅电极，同时半导体纳米线由于应力产生衬垫部分而处于纵向应力之下。由于栅极电介质和栅电极的形成锁定在半导体纳米线的应变状态，半导体纳米线的中间部分在移除应力产生衬里之后处于内置的固有纵向应力。源极和漏极区域形成在半导体焊盘中以提供半导体纳米线晶体管。中间线（MOL）电介质层可以直接形成在源极和漏极焊盘上。

10. 发明申请

US20100252800A1 NANOWIRE DEVICES FOR ENHANCING MOBILITY THROUGH STRESS ENGINEERING 有权
标题翻译：用于通过应力工程增强移动性的纳米装置
公开(公告)号：US20100252800A1
公开(公告)日：2010-10-07
申请号：US12417808
申请日：2009-04-03
申请人： Dureseti Chidambarrao , Xiao H. Liu , Lidija Sekaric
发明人： Dureseti Chidambarrao , Xiao H. Liu , Lidija Sekaric
IPC分类号： H01L29/66 , H01L21/20 , H01L27/092 , H01L21/8238
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/84 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938 , Y10S977/957
摘要： A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors.
摘要翻译：在第一半导体纳米线上形成p型半导体纳米线晶体管，在第二半导体纳米线上形成n型半导体纳米线晶体管。第一和第二半导体纳米线具有具有不同宽度与高度比的矩形横截面面积。选择每个半导体纳米线晶体管的半导体纳米线的类型，使得顶表面和底表面在具有更大宽度与高度比的半导体纳米线中提供比单元宽度更大的导通电流，而侧壁表面提供更大的具有比宽度与高度比较小的另一半导体纳米线中的顶表面和底表面的每单位宽度的电流。可以在第一和第二半导体纳米线晶体管上形成不同类型的应力产生材料层以提供相反类型的应力，这可以用于增强第一和第二半导体纳米线晶体管的导通电流。

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