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1. 发明申请

US20060024935A1 Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing 有权
标题翻译：金属硅化物通过硅<110>通道填料引起横向过度侵蚀
公开(公告)号：US20060024935A1
公开(公告)日：2006-02-02
申请号：US10903319
申请日：2004-07-30
申请人： Duofeng Yue , Peijun Chen , Sue Crank , Thomas Bonifield , Jiong-Ping Lu , Jie-Jie Xu
发明人： Duofeng Yue , Peijun Chen , Sue Crank , Thomas Bonifield , Jiong-Ping Lu , Jie-Jie Xu
IPC分类号： H01L21/28
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L29/6659
摘要： The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).
摘要翻译：本发明提供一种制造用于半导体器件（110）的金属硅化物电极（100）的方法。该方法包括将小原子注入nMOS半导体衬底（130）至nMOS半导体衬底中不大于约30纳米的深度（132）。该方法还包括在nMOS半导体衬底上沉积过渡金属层（400）。使过渡金属层和nMOS半导体衬底反应以形成金属硅化物电极。本发明的其它方面包括制造集成电路（700）的方法。

2. 发明申请

US20060024938A1 Method for reducing metal silicide excessive encroachment defects in the manufacture of a semiconductor device having silicided source/drain regions 审中-公开
标题翻译：在制造具有硅化物源极/漏极区域的半导体器件的过程中减少金属硅化物过度侵入缺陷的方法
公开(公告)号：US20060024938A1
公开(公告)日：2006-02-02
申请号：US10901697
申请日：2004-07-29
申请人： Duofeng Yue , Peijun Chen , Jiong-Ping Lu , Thomas Bonifield , Noel Russell
发明人： Duofeng Yue , Peijun Chen , Jiong-Ping Lu , Thomas Bonifield , Noel Russell
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6656 , H01L21/823814 , H01L29/665 , H01L29/6653
摘要： The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor device, and a semiconductor device. The method for manufacturing a semiconductor device, among other steps, includes forming source/drain regions (290) in a substrate (210), the source/drain regions (290) located proximate a gate structure having sidewall spacers (270) and positioned over the substrate (210), and modifying a footprint of the sidewall spacers (270) by forming protective regions (410) proximate a base of the sidewall spacers (270). The method further includes forming metal silicide regions (610) in the source/drain regions (290).
摘要翻译：本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法以及半导体器件。除了其他步骤之外，制造半导体器件的方法包括在衬底（210）中形成源极/漏极区域（290），源/漏极区域（290）位于具有侧壁间隔物（270）的栅极结构附近并定位在衬底（210），并且通过在侧壁间隔物（270）的基部附近形成保护区（410）来修改侧壁间隔物（270）的覆盖区。该方法还包括在源/漏区（290）中形成金属硅化物区（610）。

3. 发明申请

US20070049022A1 NICKEL ALLOY SILICIDE INCLUDING INDIUM AND A METHOD OF MANUFACTURE THEREFOR 有权
标题翻译：镍合金硅胶包括其中的一种和其制造方法
公开(公告)号：US20070049022A1
公开(公告)日：2007-03-01
申请号：US11551374
申请日：2006-10-20
申请人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
发明人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

4. 发明申请

US20070141840A1 Nickel silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的硅化镍及其制造方法
公开(公告)号：US20070141840A1
公开(公告)日：2007-06-21
申请号：US11678950
申请日：2007-02-26
申请人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
发明人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.
摘要翻译：本发明提供一种半导体装置及其制造方法以及包括该半导体装置的集成电路的制造方法。除了其它元件之外，半导体器件可以包括衬底（110）以及位于衬底（110）上方的硅化镍区域（170），所述硅化镍区域（170）具有位于其中的铟的量。

5. 发明申请

US20060223295A1 Nickel silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的硅化镍及其制造方法
公开(公告)号：US20060223295A1
公开(公告)日：2006-10-05
申请号：US11096660
申请日：2005-04-01
申请人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
发明人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
IPC分类号： H01L21/4763
CPC分类号： H01L21/28518 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.
摘要翻译：本发明提供一种半导体装置及其制造方法以及包括该半导体装置的集成电路的制造方法。除了其它元件之外，半导体器件可以包括衬底（110）以及位于衬底（110）上方的硅化镍区域（170），所述硅化镍区域（170）具有位于其中的铟的量。

6. 发明申请

US20060024882A1 Method for manufacturing a semiconductor device having silicided regions 有权
标题翻译：制造具有硅化物区域的半导体器件的方法
公开(公告)号：US20060024882A1
公开(公告)日：2006-02-02
申请号：US10901756
申请日：2004-07-29
申请人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas Bonifield
发明人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas Bonifield
IPC分类号： H01L21/336
CPC分类号： H01L21/823835 , H01L21/02057 , H01L21/0206 , H01L21/02068 , H01L27/0629 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).
摘要翻译：本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法。除了其他步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（120）并且在栅极结构（120）附近的衬底（110）中形成源极/漏极区域（190））。该方法还包括对栅极结构（120）和衬底（110）进行干蚀刻工艺，并且在将栅极结构（120）和衬底（120）经受栅极结构（120）和衬底（110）到干蚀刻工艺。此后，该方法包括在栅极结构（120）和氟化源极/漏极（320）中形成金属硅化物区域（510,520）。

7. 发明授权

US07402514B2 Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer 有权
标题翻译：使用用于低介电常数层间和层间（或金属间和内部）介电层的电介质衬垫的线间可靠性增强
公开(公告)号：US07402514B2
公开(公告)日：2008-07-22
申请号：US10350451
申请日：2003-01-24
申请人： Robert Tsu , Joe W. McPherson , William R. McKee , Thomas Bonifield
发明人： Robert Tsu , Joe W. McPherson , William R. McKee , Thomas Bonifield
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.
摘要翻译：本发明的一个实施例是一种在第一导体和第二导体之间提供连接的方法，其中第一导体位于第二导体下方并由第一绝缘层分开，该方法包括以下步骤：在第一绝缘层（图1-4的层124或128），开口具有顶部，底部和侧壁，并且位于第一导体和第二导体之间; 仅在开口的侧壁上形成第二绝缘层（图3和4的层134,138和142），从而在第一绝缘层中留下较小的开口; 在较小的开口中形成导电材料（图3和图4的材料140）并且其中所述第一绝缘层由低k材料构成，并且所述第二绝缘层由具有小于所述第一绝缘层的漏电特性的漏电特性的绝缘体构成。

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