专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130264688A1 METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT SYSTEM WITH INTERCONNECTED STACKED DEVICE WAFERS 审中-公开
标题翻译：提供具有互连堆叠器件波形的集成电路系统的方法和装置
公开(公告)号：US20130264688A1
公开(公告)日：2013-10-10
申请号：US13441627
申请日：2012-04-06
申请人： Yin Qian , Hsin-Chih Tai , Duli Mao , Tiejun Dai , Howard E. Rhodes , Hongli Yang
发明人： Yin Qian , Hsin-Chih Tai , Duli Mao , Tiejun Dai , Howard E. Rhodes , Hongli Yang
IPC分类号： H01L29/06 , H01L21/28
CPC分类号： H01L24/80 , H01L21/76898 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/14634 , H01L2224/04042 , H01L2224/05567 , H01L2224/05571 , H01L2224/08145 , H01L2224/2401 , H01L2224/24105 , H01L2224/24147 , H01L2224/48151 , H01L2224/73251 , H01L2224/80357 , H01L2224/80896 , H01L2224/80986 , H01L2224/82031 , H01L2224/82106 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/3511 , H01L2224/80001 , H01L2924/00012 , H01L2224/05552
摘要： An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer.
摘要翻译：集成电路系统包括具有靠近第一金属层的第一半导体层的第一器件晶片，第一金属层包括设置在第一金属层氧化物内的第一导体。还包括具有靠近第二金属层的第二半导体层的第二器件晶片，该第二金属层包括设置在第二金属层氧化物内的第二导体。在第一金属层氧化物和第二金属层氧化物之间的氧化物接合界面处，第一金属层氧化物的前侧结合到第二金属层氧化物的前侧。导电路径将第一导体耦合到第二导体，导电材料形成在蚀刻在第一导体和第二导体之间的空腔中，并通过氧化物接合界面从第二器件晶片的背面蚀刻穿过第二半导体层。

2. 发明申请

US20140014813A1 INTEGRATED CIRCUIT STACK WITH INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELDING 有权
标题翻译：具有集成电磁干扰屏蔽的集成电路堆栈
公开(公告)号：US20140014813A1
公开(公告)日：2014-01-16
申请号：US13547997
申请日：2012-07-12
申请人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
发明人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
IPC分类号： H01L23/552 , H01L27/146
CPC分类号： H01L27/14623 , H01L27/14634 , H01L27/1464 , H01L27/1469
摘要： An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
摘要翻译：集成电路系统包括具有靠近第一金属层的第一半导体层的第一器件晶片，第一金属层包括设置在第一金属层氧化物内的第一导体。具有靠近包括第二导体的第二金属层的第二半导体层的第二器件晶片设置在第二金属层氧化物内。第一器件晶片的前端在接合界面处结合到第二器件晶片的前侧。导电路径通过接合界面将第一导体耦合到第二导体。第一金属EMI屏蔽设置在第一金属氧化物层和第二金属层氧化物层之一中。第一EMI屏蔽包括在最靠近接合界面的第一金属氧化物层和第二金属层氧化物层中的所述一个的金属层中。

3. 发明授权

US08933544B2 Integrated circuit stack with integrated electromagnetic interference shielding 有权
标题翻译：具有集成电磁干扰屏蔽的集成电路堆栈
公开(公告)号：US08933544B2
公开(公告)日：2015-01-13
申请号：US13547997
申请日：2012-07-12
申请人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
发明人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
IPC分类号： H01L23/552 , H01L27/146
CPC分类号： H01L27/14623 , H01L27/14634 , H01L27/1464 , H01L27/1469
摘要： An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
摘要翻译：集成电路系统包括具有靠近第一金属层的第一半导体层的第一器件晶片，第一金属层包括设置在第一金属层氧化物内的第一导体。具有靠近包括第二导体的第二金属层的第二半导体层的第二器件晶片设置在第二金属层氧化物内。第一器件晶片的前端在接合界面处结合到第二器件晶片的前侧。导电路径通过接合界面将第一导体耦合到第二导体。第一金属EMI屏蔽设置在第一金属氧化物层和第二金属层氧化物层之一中。第一EMI屏蔽包括在最靠近接合界面的第一金属氧化物层和第二金属层氧化物层中的所述一个的金属层中。

4. 发明申请

US20070018264A1 Optimized image sensor process and structure to improve blooming 审中-公开
标题翻译：优化图像传感器的工艺和结构，提高开花度
公开(公告)号：US20070018264A1
公开(公告)日：2007-01-25
申请号：US11210996
申请日：2005-08-24
申请人： Howard Rhodes , Hidetoshi Nozaki , Sohei Manabe , Hsin-chih Tai , Satyadev Nagaraja , Ashish Shah , William Qian , Hongli Yang , Tiejun Dai
发明人： Howard Rhodes , Hidetoshi Nozaki , Sohei Manabe , Hsin-chih Tai , Satyadev Nagaraja , Ashish Shah , William Qian , Hongli Yang , Tiejun Dai
IPC分类号： H01L31/0232
CPC分类号： H01L27/14689 , H01L27/1463 , H01L27/14654
摘要： An image sensor that has a pixel array using an isolation structure between pixels that reduce electrical cross-talk is disclosed. The pixel array is formed on a substrate that has a thin (less than 5 microns) epitaxial layer. The isolation structure uses a deep p-well to surround a shallow trench isolation. The deep p-well is formed using an implant energy of typically over 700 keV.
摘要翻译：公开了一种使用减少电串扰的像素之间的隔离结构的像素阵列的图像传感器。像素阵列形成在具有薄（小于5微米）外延层的衬底上。隔离结构使用深p阱来围绕浅沟槽隔离。使用典型地超过700keV的注入能量形成深p阱。

5. 发明申请

US20090201400A1 Backside illuminated image sensor with global shutter and storage capacitor 审中-公开
标题翻译：具有全局快门和存储电容器的背面照明图像传感器
公开(公告)号：US20090201400A1
公开(公告)日：2009-08-13
申请号：US12028659
申请日：2008-02-08
申请人： Guangbin Zhang , Tiejun Dai , Hongli Yang
发明人： Guangbin Zhang , Tiejun Dai , Hongli Yang
IPC分类号： H04N5/335 , H01L27/148
CPC分类号： H04N5/335 , H01L27/14609 , H01L27/14627 , H01L27/1464 , H04N5/3745
摘要： A backside illuminated imaging sensor pixel includes a photodiode region, a pixel circuitry region, and a storage capacitor. The photodiode region is disposed within a semiconductor die for accumulating an image charge. The pixel circuitry region is disposed on the semiconductor die between a frontside of the semiconductor die and the photodiode region. The pixel circuitry region overlaps at least a portion of the photodiode region. The storage capacitor is included within the pixel circuitry region overlapping the photodiode region and is selectively coupled to the photodiode region to temporarily store image charges accumulated thereon.
摘要翻译：背面照明成像传感器像素包括光电二极管区域，像素电路区域和存储电容器。光电二极管区域设置在用于累积图像电荷的半导体管芯内。像素电路区域设置在半导体管芯的前半部分与光电二极管区域之间的半导体管芯上。像素电路区域与光电二极管区域的至少一部分重叠。存储电容器包括在与光电二极管区域重叠的像素电路区域内，并且选择性地耦合到光电二极管区域以暂时存储其上累积的图像电荷。

6. 发明授权

US07105878B2 Active pixel having reduced dark current in a CMOS image sensor 有权
标题翻译：有源像素在CMOS图像传感器中具有降低的暗电流
公开(公告)号：US07105878B2
公开(公告)日：2006-09-12
申请号：US10945538
申请日：2004-09-20
申请人： Xinping He , Chih-Huei Wu , Hongli Yang
发明人： Xinping He , Chih-Huei Wu , Hongli Yang
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14643 , H01L27/1463
摘要： The active pixel includes a photodiode, a reset transistor, and a pixel output transistor. The photodiode is substantially covered with a protective structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. The protective structure has a photodiode contact formed therein to electrically connect the photodiode to the pixel output transistor.
摘要翻译：有源像素包括光电二极管，复位晶体管和像素输出晶体管。光电二极管基本上覆盖有保护结构，从而保护光电二极管的整个表面免受损坏。这实质上消除了潜在的漏电流源，这导致暗电流。保护结构具有形成在其中的光电二极管接头，以将光电二极管电连接到像素输出晶体管。

7. 发明授权

US06953923B2 CMOS image sensor having reduced numbers of column readout circuits 有权
标题翻译： CMOS图像传感器具有减少数量的列读出电路
公开(公告)号：US06953923B2
公开(公告)日：2005-10-11
申请号：US10368949
申请日：2003-02-18
申请人： Hongli Yang , Xinping He
发明人： Hongli Yang , Xinping He
IPC分类号： H04N5/363 , H04N5/365 , H04N5/374 , H04N5/378 , H01L27/00
CPC分类号： H04N5/3742
摘要： The image sensor includes a first group and a second group of column readout circuits for reading out pixel signals from said pixels. The total number of column readout circuits in each group is substantially less than the number of columns in the image sensor pixel array. Further included is a multiplexer bus system having selection switches for selectively switching pixel signals from a block of pixels in a column as input into the first group of column readout circuits. The multiplexer bus system also selectively switches pixel signals from another block of pixels in a column as input into a second group of column readout circuits. However, when the first group of column readout circuits is reading and storing said pixel signals, the second group of column readout circuits is transferring out the processed signals. Thus, the first and second groups work alternately.
摘要翻译：图像传感器包括用于从所述像素读出像素信号的第一组和第二组列读出电路。每组中列读出电路的总数显着小于图像传感器像素阵列中的列数。进一步包括的多路复用器总线系统具有选择开关，用于选择性地将来自列中的像素块的像素信号作为输入切换到第一组列读出电路。多路复用器总线系统还选择性地将作为输入的列中的另一个像素块的像素信号切换成第二组列读出电路。然而，当第一组列读出电路正在读取并存储所述像素信号时，第二组列读出电路正在转出处理的信号。因此，第一组和第二组交替工作。

8. 发明申请

US20050062085A1 Active pixel having reduced dark current in a CMOS image sensor 有权
标题翻译：有源像素在CMOS图像传感器中具有降低的暗电流
公开(公告)号：US20050062085A1
公开(公告)日：2005-03-24
申请号：US10945538
申请日：2004-09-20
申请人： Xinping He , Chih-Huei Wu , Hongli Yang
发明人： Xinping He , Chih-Huei Wu , Hongli Yang
IPC分类号： H01L27/146 , H01L31/062
CPC分类号： H01L27/14643 , H01L27/1463
摘要： The active pixel includes a photodiode, a reset transistor, and a pixel output transistor. The photodiode is substantially covered with a protective structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. The protective structure has a photodiode contact formed therein to electrically connect the photodiode to the pixel output transistor.
摘要翻译：有源像素包括光电二极管，复位晶体管和像素输出晶体管。光电二极管基本上覆盖有保护结构，从而保护光电二极管的整个表面免受损坏。这实质上消除了潜在的漏电流源，这导致暗电流。保护结构具有形成在其中的光电二极管接头，以将光电二极管电连接到像素输出晶体管。

9. 发明授权

US06707496B1 CMOS sensor having analog delay line for image processing 有权
标题翻译： CMOS传感器具有用于图像处理的模拟延迟线
公开(公告)号：US06707496B1
公开(公告)日：2004-03-16
申请号：US09397634
申请日：1999-09-15
申请人： Hongli Yang , Xinping He , Datong Chen
发明人： Hongli Yang , Xinping He , Datong Chen
IPC分类号： H04N314
CPC分类号： H04N9/045 , G11C27/04 , H04N5/3743
摘要： The present invention is directed to an analog delay line for a color CMOS image sensor which is compatible with MOS fabrication technology. The invention allows for the simultaneous reading of pixel signals from two rows of pixels so that combinations of signals from pixels in different rows may be obtained. The delay line includes a set of storage capacitors on which the pixel signals are stored, and a means for writing the signals from the pixels onto the capacitors in sequence. The stored analog pixel signals may then be read out from the delay line at the appropriate time so that they may be combined with pixel signals from adjacent pixels in different rows. In one embodiment, two delay lines are used, so that pixel signals from a current row can be written into one delay line, while the pixel signals from a previous row are being read out from the other delay line. In another embodiment, a single delay line is used in combination with a single pixel delay circuit. When the single pixel delay circuit is used, the pixel signals from a previous row are read out from the delay line and temporarily stored in the single pixel delay circuit, one at a time, shortly after which the pixel signals from the next row are written into the delay line. The pixel signals from the single pixel delay circuit are then read out at the same time that the pixel signals from the next row are being read in, so that signals from adjacent pixels in adjacent rows are available to the processing circuitry at the same time.
摘要翻译：本发明涉及一种与MOS制造技术兼容的彩色CMOS图像传感器的模拟延迟线。本发明允许从两行像素同时读取像素信号，从而可以获得来自不同行中的像素的信号的组合。延迟线包括存储像素信号的一组存储电容器，以及用于将来自像素的信号依次写入电容器的装置。然后可以在适当的时间从延迟线读出存储的模拟像素信号，使得它们可以与来自不同行中的相邻像素的像素信号组合。在一个实施例中，使用两个延迟线，使得来自当前行的像素信号可以写入一个延迟线，而来自前一行的像素信号正在从另一延迟线读出。在另一个实施例中，单个延迟线与单个像素延迟电路组合使用。当使用单像素延迟电路时，从延迟线读出来自前一行的像素信号，并在不久之前暂时存储在单个像素延迟电路中，之后不久将来自下一行的像素信号被写入进入延迟线。来自单个像素延迟电路的像素信号在与下一行的像素信号正被读入的同时被读出，从而来自相邻行中相邻像素的信号同时可用于处理电路。

10. 发明授权

US07667169B2 Image sensor with simultaneous auto-focus and image preview 有权
标题翻译：图像传感器同时进行自动对焦和图像预览
公开(公告)号：US07667169B2
公开(公告)日：2010-02-23
申请号：US12125829
申请日：2008-05-22
申请人： Hongli Yang , Hongjun Li , Xinping He
发明人： Hongli Yang , Hongjun Li , Xinping He
IPC分类号： G02B7/04 , G02B27/40 , G02B27/64
CPC分类号： H04N5/23212 , G02B7/28 , H01L27/14641 , H04N5/3742
摘要： Embodiments of the present invention are directed to a plurality of light sensor cells disposed in a substrate in a shared pixel arrangement. Common readout circuitry is used to simultaneously read out image information from a group of light sensor cells. The image information from the group of light sensor cells is added together simultaneously and coupled to auto-focus circuitry and/or preview circuitry to provide for better lens adjustments and preview display.
摘要翻译：本发明的实施例涉及在共享像素布置中设置在基板中的多个光传感器单元。公共读出电路用于同时从一组光传感器单元读出图像信息。来自一组光传感器单元的图像信息被同时加在一起并耦合到自动对焦电路和/或预览电路以提供更好的镜头调整和预览显示。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式