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1. 发明授权

US5440258A Off-chip driver with voltage regulated predrive 失效
标题翻译：片外驱动器具有电压调节预制
公开(公告)号：US5440258A
公开(公告)日：1995-08-08
申请号：US193317
申请日：1994-02-08
申请人： Duane E. Galbi , Russell J. Houghton , Michael Killian , Adam B. Wilson
发明人： Duane E. Galbi , Russell J. Houghton , Michael Killian , Adam B. Wilson
IPC分类号： G11C11/407 , G11C11/409 , H03K19/003 , H03K3/01
CPC分类号： H03K19/00361 , H03K19/00384
摘要： An off-chip driver with regulated supplies compensates for power supply fluctuations. The circuit reduces di/dt noise by providing complementary voltage regulators to regulate the high and low supplies to the driver stages such that they see a constant operating voltage regardless of changes in supply voltage, V.sub.CC. The circuit uses two push-pull stages which charge and discharge the output load capacitance, C.sub.0. This regulated voltage to the driver stages reduces di/dt noise and provides a constant overdrive voltage, constant gate slew rate, and constant staging delay over a specified external supply voltage range.
摘要翻译：具有稳压电源的片外驱动器补偿电源波动。该电路通过提供互补的电压调节器来调节di / dt噪声，以调节驱动级的高电平和低电耗，使得它们看到恒定的工作电压，而不管电源电压VCC如何变化。该电路使用两个推挽级，用于对输出负载电容C0进行充电和放电。驱动级的这种调节电压会降低di / dt噪声，并提供恒定的过驱动电压，恒定栅极转换速率以及在指定的外部电源电压范围内的恒定分段延迟。

2. 发明申请

US20070223302A1 Reducing leakage current in memory device using bitline isolation 失效
标题翻译：使用位线隔离减少存储器件中的漏电流
公开(公告)号：US20070223302A1
公开(公告)日：2007-09-27
申请号：US11387879
申请日：2006-03-24
申请人： Andre Sturm , Christopher Miller , Wolfgang Hokenmaier , Michael Killian , Jochen Hoffman
发明人： Andre Sturm , Christopher Miller , Wolfgang Hokenmaier , Michael Killian , Jochen Hoffman
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/02 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.
摘要翻译：一种用于减少包括多个存储体的半导体存储器件中的缺陷漏电流的方法，每个存储体包括多个存储器阵列和包括多个读出放大器的读出放大器列，其中存在位于并共享的读出放大器列由存储器阵列的对立面。根据存储体中的异常位线泄漏的存在和位置，独立地为多个存储体中的每一个存储至少一个存储体特定的隔离控制信号。所述至少一个存储体特定的隔离控制信号被提供给相应的存储体中的至少一个读出放大器列，以将至少一个侧面隔离到相应的存储体中处于未选择状态的至少一个存储器阵列。

3. 发明申请

US20090283984A1 Two wheel streering bicycle with each wheel having its own steering control operated by rider's left and right hand respectively and rider positioned facing an angle greater than zero and less than ninty degrees with respect to the direction of motion 有权
公开(公告)号：US20090283984A1
公开(公告)日：2009-11-19
申请号：US12152218
申请日：2008-05-14
申请人： Michael Killian
发明人： Michael Killian
IPC分类号： B62K21/00
CPC分类号： B62K3/02 , B62K3/002 , B62K21/00
摘要： A two wheel steering bicycle with two steering controls and rider positioned facing an angle greater than zero and less than ninety degrees with respect to the direction of motion. A frame member connects the rear head tube to the front head tube. The rear wheel attaches to the rear fork extending upwards. The rear fork steerer column passes through the rear head tube and can rotate within the rear head tube by means of a bicycle bearing headset. A rear steering handle is connected to the rear fork steerer column. The rear steering handle is designed to contact the rider's first hand. The front wheel attaches to the front fork extending upwards. The front fork steerer column passes through the front head tube and can rotate within the front head tube by means of a bicycle bearing headset. A front steering handle is connected to the front fork steerer column. The front steering handle is designed to contact the rider's second hand. A seat tube member attaches to the frame member. A bicycle saddle is attached to the seat tube member in such a way as to position the rider facing an angle greater than zero and less than ninety degrees with respect to the longitudinal axis of the frame member. A bicycle bottom bracket, front sprocket, left and right crank and pedals are attached to the device. The rider's left hand is positioned at the rider's left side and contacts one of the steering handles. The rider's right hand is positioned at the rider's right side and contacts the other steering handle. The saddle and steering handles should be adjusted so that the rider's body is roughly balanced across the vertical plane of the rear and front wheels. The device moves forward and the rider keeps the device balanced by constantly correcting the front and rear steering handles. It may take some practice to make this correction reflex, but once mastered this device offers more control and artistic expression than a currently available bicycle.

4. 发明授权

US6049492A Interleaved sense amplifier with a single-sided precharge device 失效
标题翻译：具有单面预充电装置的交错式读出放大器
公开(公告)号：US6049492A
公开(公告)日：2000-04-11
申请号：US107191
申请日：1998-06-29
申请人： Thomas Vogelsang , Michael Killian
发明人： Thomas Vogelsang , Michael Killian
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C7/12 , G11C7/06
摘要： An interleaved sense amplifier with a single sided precharge device which provides simplification of the conventional sense amplifier circuitry, as well as a reduction in the area occupied by the sense amplifier circuitry, thereby resulting in chip size reduction. A precharge device is placed on only one side of the sense amplifier, which is used to charge both sets of bit lines pairs that are coupled to the sense amplifier to a common voltage during an equalization/precharge operation. In addition, the resistance of the transistors comprising the precharge device is increased such that the precharge transistors can be further utilized for limiting the flow of current between the bit line pair and precharge net, which obviates the need for the additional leakage limiter devices in the conventional sense amplifier arrangement. Thus, a compact and simplified sense amplifier architecture is realized.
摘要翻译：具有单面预充电装置的交错读出放大器，其提供常规读出放大器电路的简化，以及减少由读出放大器电路占据的面积，从而导致芯片尺寸减小。预充电装置仅放置在读出放大器的一侧，其用于在均衡/预充电操作期间将耦合到读出放大器的两组位线对充电至公共电压。此外，包括预充电装置的晶体管的电阻增加，使得可以进一步利用预充电晶体管来限制位线对和预充电网之间的电流流动，这避免了在该位置线对和预充电网之间的附加泄漏限制器件的需要常规读出放大器布置。因此，实现了紧凑且简化的读出放大器架构。

5. 发明申请

US20080151647A1 Programmable Sense Amplifier Multiplexer Circuit with Dynamic Latching Mode 失效
标题翻译：具有动态锁存模式的可编程灵敏放大器多路复用器电路
公开(公告)号：US20080151647A1
公开(公告)日：2008-06-26
申请号：US11615118
申请日：2006-12-22
申请人： Christopher Miller , Michael Killian
发明人： Christopher Miller , Michael Killian
IPC分类号： G11C7/08 , G11C7/00
CPC分类号： G11C11/406 , G11C7/08 , G11C7/12 , G11C11/40615 , G11C11/4091 , G11C11/4094 , G11C2207/005
摘要： Multiplexer control logic is provided for a semiconductor memory device that combines the function of programmable disconnect-state with a dynamic or dynamic latching mode that operates during self-refresh. The programmable disconnect state disconnects the sense amplifier from a memory array segment when it is unselected. When a memory array segment is being accessed, (such as during self-refresh), the multiplexers are latched into a selected state thereby eliminating the multiplexer switching current while the memory array segment is being accessed.
摘要翻译：为半导体存储器件提供多路复用器控制逻辑，其将可编程断开状态的功能与在自刷新期间操作的动态或动态锁存模式相结合。当未选择时，可编程断开状态会将读出放大器与存储器阵列段断开。当存储器阵列段被访问时（例如在自刷新期间），多路复用器被锁存到选择的状态，从而在访问存储器阵列段时消除多路转换器切换电流。

6. 发明申请

US20070165439A1 Edge pad architecture for semiconductor memory 失效
标题翻译：半导体存储器的边缘焊盘结构
公开(公告)号：US20070165439A1
公开(公告)日：2007-07-19
申请号：US11320266
申请日：2005-12-28
申请人： Josef Schnell , Michael Richter , Michael Killian
发明人： Josef Schnell , Michael Richter , Michael Killian
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , H01L27/105
摘要： A memory includes a wafer having at least a first and second edge, at least one memory bank array, a data path, and a plurality of data pads. The data path is coupled to the memory bank array. The plurality of data pads are coupled to the data path and configured with the data path to bus data to and from the memory bank array. The data pads are further configured such that each of the data pads are located adjacent the first and second edges of the wafer. The memory component is configurable for alternative applications such that in a first application all of the data pads used to bus data are located only on the first edge of the wafer and such that in a second application at least one of the data pads used to bus data is located on the first edge of the wafer and at least one of the data pads used to bus data is located on the second edge of the wafer.
摘要翻译：存储器包括具有至少第一和第二边缘，至少一个存储体阵列，数据路径和多个数据焊盘的晶片。数据路径耦合到存储体阵列。多个数据焊盘耦合到数据路径并配置有与存储体阵列的总线数据的数据路径。数据焊盘被进一步配置成使得每个数据焊盘位于晶片的第一和第二边缘附近。存储器组件可配置用于替代应用，使得在第一应用中，用于总线数据的所有数据焊盘仅位于晶片的第一边缘上，并且使得在第二应用中，至少一个数据焊盘用于总线数据位于晶片的第一边缘上，并且用于总线数据的至少一个数据焊盘位于晶片的第二边缘上。

7. 发明申请

US20050134017A1 Two wheel steering bicycle with each wheel having its own steering control operated by rider's left and right hand respectively and rider positioned facing the direction of motion 失效
公开(公告)号：US20050134017A1
公开(公告)日：2005-06-23
申请号：US10745437
申请日：2003-12-23
申请人： Michael Killian
发明人： Michael Killian
IPC分类号： B62K17/00 , B62K21/00
CPC分类号： B62K21/00 , B62K17/00
摘要： A two wheel steering bicycle with two steering controls and rider positioned facing forward. A top tube member connects the rear head tube to the front head tube. The rear wheel attaches to the rear fork extending upwards. The rear fork steerer column passes through the rear head tube and can rotate within the rear head tube by means of a bicycle bearing headset. A rear steering handle is connected to the rear fork steerer column. The rear steering handle is designed to contact the rider's first hand. The front wheel attaches to the front fork extending upwards. The front fork steerer column passes through the front head tube and can rotate within the front head tube by means of a bicycle bearing headset. A front steering handle is connected to the front fork steerer column. The front steering handle is designed to contact the rider's second hand. A seat tube member attaches to the top tube member. A bicycle saddle is attached to the seat tube member in such a way as to position the rider facing forward parallel to the longitudinal axis of the top tube member. A bicycle bottom bracket, front sprocket, left and right crank and pedals are attached to the device. The rider's left hand is positioned at the rider's left side and contacts one of the steering handles. The rider's right hand is positioned at the rider's right side and contacts the other steering handle. The saddle and steering handles should be adjusted so that the rider's body is roughly balanced across the vertical plane of the rear and front wheels. The device moves forward and the rider keeps the device balanced by constantly correcting the front and rear steering handles. It may take some practice to make this correction reflex, but once mastered this device offers more control and artistic expression than a currently available bicycle.

8. 发明授权

US06598892B1 Two wheel steering bicycle with latitudinal aligned wheels 失效
公开(公告)号：US06598892B1
公开(公告)日：2003-07-29
申请号：US10040921
申请日：2002-01-07
申请人： Michael Killian
发明人： Michael Killian
IPC分类号： B62K1700
CPC分类号： B62K21/00
摘要： A center support member connects the rear head tube to the front head tube. The rear wheel attaches to the rear fork extending upwards. The rear fork steerer column passes through the rear head tube and can rotate within the rear head tube by a bicycle bearing headset. A rear steering handle is connected to the rear fork steerer column. The rear steering handle is designed to contact the rider's lower arm and hand. The front wheel attaches to the front fork extending upwards. The front fork steerer column passes through the front head tube and can rotate within the front head tube by a bicycle bearing headset. A front steering handle is connected to the front fork steerer column. The front steering handle is designed to contact the rider's lower arm and hand. A rider support member attaches to the center support member extending downward. A bicycle saddle is attached to the rider support member in such a way as to position the rider facing perpendicular to the longitudinal axis of the center support member. A bicycle bottom bracket, front sprocket, left and right crank and pedals are attached to the bottom of the rider support member. The front sprocket is positioned perpendicular to the longitudinal axis of the center support member. The rider is positioned perpendicular to the longitudinal axis of the center support member. The rider's left arm is positioned at the user's left side and contacts the rear steering handle. The rider's right arm is positioned at the user's right side and contacts the front steering handle. The device moves forward to the rider's right. The saddle and steering handles should be adjusted so that the rider's body is roughly balanced across the vertical plane of the rear and front wheels. The device moves to the right and the rider keeps the device balanced by constantly correcting the coordinated rear and front steering systems. It may take some practice to make this correction reflex, but once mastered this device offers more control and artistic expression than a currently available bicycle.

9. 发明授权

US07492648B2 Reducing leakage current in memory device using bitline isolation 失效
标题翻译：使用位线隔离减少存储器件中的漏电流
公开(公告)号：US07492648B2
公开(公告)日：2009-02-17
申请号：US11387879
申请日：2006-03-24
申请人： Andre Sturm , Christopher Miller , Wolfgang Hokenmaier , Michael Killian , Jochen Hoffman
发明人： Andre Sturm , Christopher Miller , Wolfgang Hokenmaier , Michael Killian , Jochen Hoffman
IPC分类号： G11C7/08 , G11C8/12
CPC分类号： G11C8/12 , G11C7/02 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.
摘要翻译：一种用于减少包括多个存储体的半导体存储器件中的缺陷漏电流的方法，每个存储体包括多个存储器阵列和包括多个读出放大器的读出放大器列，其中存在位于并共享的读出放大器列由存储器阵列的对立面。根据存储体中的异常位线泄漏的存在和位置，独立地为多个存储体中的每一个存储至少一个存储体特定的隔离控制信号。所述至少一个存储体特定的隔离控制信号被提供给相应的存储体中的至少一个读出放大器列，以将至少一个侧面隔离到相应的存储体中处于未选择状态的至少一个存储器阵列。

10. 发明授权

US07443751B2 Programmable sense amplifier multiplexer circuit with dynamic latching mode 失效
标题翻译：具有动态锁存模式的可编程读出放大器多路复用器电路
公开(公告)号：US07443751B2
公开(公告)日：2008-10-28
申请号：US11615118
申请日：2006-12-22
申请人： Christopher Miller , Michael Killian
发明人： Christopher Miller , Michael Killian
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/08 , G11C7/12 , G11C11/40615 , G11C11/4091 , G11C11/4094 , G11C2207/005
摘要： Multiplexer control logic is provided for a semiconductor memory device that combines the function of programmable disconnect-state with a dynamic or dynamic latching mode that operates during self-refresh. The programmable disconnect state disconnects the sense amplifier from a memory array segment when it is unselected. When a memory array segment is being accessed, (such as during self-refresh), the multiplexers are latched into a selected state thereby eliminating the multiplexer switching current while the memory array segment is being accessed.
摘要翻译：为半导体存储器件提供多路复用器控制逻辑，其将可编程断开状态的功能与在自刷新期间操作的动态或动态锁存模式相结合。当未选择时，可编程断开状态会将读出放大器与存储器阵列段断开。当存储器阵列段被访问时（例如在自刷新期间），多路复用器被锁存到选择的状态，从而在访问存储器阵列段时消除多路开关电流。

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