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1. 发明授权

US07635641B2 Integrated circuit support structures and their fabrication 有权
标题翻译：集成电路支持结构及其制造
公开(公告)号：US07635641B2
公开(公告)日：2009-12-22
申请号：US11250421
申请日：2005-10-17
申请人： Dror Hurwitz , Mardechay Farkash , Eva Igner , Amit Zeidler , Boris Statnikov , Benny Michaeli
发明人： Dror Hurwitz , Mardechay Farkash , Eva Igner , Amit Zeidler , Boris Statnikov , Benny Michaeli
IPC分类号： H01L21/44
CPC分类号： H05K3/4647 , H01L21/4857 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H05K3/108 , H05K3/205 , H05K3/388 , H05K3/423 , H05K3/4682 , H05K2201/096 , H05K2203/0152 , H05K2203/0384 , H05K2203/0733 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto.
摘要翻译：一种制造电子基板的方法，包括以下步骤：（A）选择第一基层; （B）在所述第一基底层上沉积第一耐蚀刻阻挡层; （C）建立交替导电层和绝缘层的前半层叠层，所述导电层通过绝缘层互连，（D）将第二基层施加到所述第一半叠层上; （F）将光致抗蚀剂的保护涂层施加到第二基层; （F）蚀刻掉第一基层; （G）去除光致抗蚀剂的保护涂层; （H）去除第一耐蚀刻阻挡层; （I）构建交替导电层和绝缘层的第二半叠层，所述导电层通过绝缘层互连，其中所述第二半堆叠具有基本对称的层叠到所述第一半堆叠; （J）将绝缘层施加到交替导电层和绝缘层的第二霍尔堆叠上，（K）去除第二基层，和（L）通过暴露堆叠的外表面上的通孔的端部并施加端接到此。

2. 发明申请

US20070082501A1 Novel integrated circuit support structures and their fabrication 有权
标题翻译：新型集成电路支持结构及其制造
公开(公告)号：US20070082501A1
公开(公告)日：2007-04-12
申请号：US11250421
申请日：2005-10-17
申请人： Dror Hurwitz , Mardechay Farkash , Eva Igner , Amit Zeidler , Boris Statnikov , Benny Michaeli
发明人： Dror Hurwitz , Mardechay Farkash , Eva Igner , Amit Zeidler , Boris Statnikov , Benny Michaeli
IPC分类号： H01L21/31 , H01L21/331 , H01L21/8222 , H01L31/00 , H01L29/739 , H01L21/469
CPC分类号： H05K3/4647 , H01L21/4857 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H05K3/108 , H05K3/205 , H05K3/388 , H05K3/423 , H05K3/4682 , H05K2201/096 , H05K2203/0152 , H05K2203/0384 , H05K2203/0733 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto.
摘要翻译：一种制造电子基板的方法，包括以下步骤：（A）选择第一基层; （B）在所述第一基底层上沉积第一耐蚀刻阻挡层; （C）建立交替导电层和绝缘层的前半层叠层，所述导电层通过绝缘层互连，（D）将第二基层施加到所述第一半叠层上; （F）将光致抗蚀剂的保护涂层施加到第二基层; （F）蚀刻掉第一基层; （G）去除光致抗蚀剂的保护涂层; （H）去除第一耐蚀刻阻挡层; （I）构建交替导电层和绝缘层的第二半叠层，所述导电层通过绝缘层互连，其中所述第二半堆叠具有基本对称的层叠到所述第一半堆叠; （J）将绝缘层施加到交替导电层和绝缘层的第二霍尔堆叠上，（K）去除第二基层，和（L）通过暴露堆叠的外表面上的通孔的端部并施加端接到此。

3. 发明申请

US20070281471A1 Advanced Multilayered Coreless Support Structures and their Fabrication 有权
标题翻译：高级多层无芯支撑结构及其制造
公开(公告)号：US20070281471A1
公开(公告)日：2007-12-06
申请号：US11421600
申请日：2006-06-01
申请人： Dror Hurwitz , Mordechay Farkash , Eva Igner , Boris Statnikov , Benny Michaeli
发明人： Dror Hurwitz , Mordechay Farkash , Eva Igner , Boris Statnikov , Benny Michaeli
IPC分类号： H01L21/4763
CPC分类号： H05K3/4647 , H01L21/4857 , H01L23/49822 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/32225 , H01L2224/45015 , H01L2224/48227 , H01L2224/48228 , H01L2224/48472 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H05K3/205 , H05K3/423 , H05K3/4682 , H05K2201/096 , H05K2203/0733 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/01004 , H01L2924/01033
摘要： A method of fabricating a free standing membrane comprising a via array in a dielectric for use as a precursor in the construction of superior electronic support structures, comprising the stages: I—Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier, and II—Detaching the membrane from the sacrificial carrier to form a free standing laminated array, and a method of fabricating an electronic substrate based on such a membrane comprising at least the stages of: (I) Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier; (II) Detaching the membrane from the sacrificial carrier to form a free standing laminated array; (V) Thinning and planarizing, and (VII) Terminating.
摘要翻译：一种制造独立式隔离膜的方法，该方法包括电介质中的通孔阵列，以用作优良电子支撑结构的构造中的前体，其包括以下步骤：I制造包含在牺牲载体上的电介质环绕中的导电通孔的膜，和II-从牺牲载体上分离膜以形成自立式层压阵列，以及基于这种膜制造电子基板的方法，至少包括以下阶段：（I）在电介质中制造包含导电通孔的膜围绕在牺牲载体上; （II）从牺牲载体上分离膜以形成独立的层压阵列; （V）稀化和平面化，和（VII）终止。

4. 发明授权

US07682972B2 Advanced multilayer coreless support structures and method for their fabrication 有权
标题翻译：高级多层无芯支撑结构及其制造方法
公开(公告)号：US07682972B2
公开(公告)日：2010-03-23
申请号：US11421600
申请日：2006-06-01
申请人： Dror Hurwitz , Mordechay Farkash , Eva Igner , Boris Statnikov , Benny Michaeli
发明人： Dror Hurwitz , Mordechay Farkash , Eva Igner , Boris Statnikov , Benny Michaeli
IPC分类号： H01L21/44
CPC分类号： H05K3/4647 , H01L21/4857 , H01L23/49822 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/32225 , H01L2224/45015 , H01L2224/48227 , H01L2224/48228 , H01L2224/48472 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H05K3/205 , H05K3/423 , H05K3/4682 , H05K2201/096 , H05K2203/0733 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/01004 , H01L2924/01033
摘要： A method of fabricating a free standing membrane including via array in a dielectric for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing laminated array, followed by terminating.
摘要翻译：制造在电介质中包括通孔阵列的独立的隔离膜的方法用作在优异的电子支撑结构的结构中作为前体，包括在牺牲载体上的电介质环绕中制造导电通孔的膜的步骤，膜从牺牲载体形成独立的层压阵列。可以通过使叠层阵列变薄平坦化，然后终止来形成基于这种自立式膜的电子基板。

5. 发明授权

US07669320B2 Coreless cavity substrates for chip packaging and their fabrication 有权
标题翻译：用于芯片封装的无芯腔基板及其制造
公开(公告)号：US07669320B2
公开(公告)日：2010-03-02
申请号：US11737269
申请日：2007-04-19
申请人： Dror Hurwitz , Mordechay Farkash , Eva Igner , Boris Statnikov , Benny Michaeli
发明人： Dror Hurwitz , Mordechay Farkash , Eva Igner , Boris Statnikov , Benny Michaeli
IPC分类号： H05K3/10
CPC分类号： H01L21/4857 , H01L21/4864 , H01L23/13 , H01L23/49822 , H01L24/48 , H01L2221/68345 , H01L2224/16225 , H01L2224/16235 , H01L2224/48095 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H05K1/183 , H05K3/06 , H05K3/205 , H05K3/4647 , H05K3/4682 , H05K3/4697 , H05K2203/0733 , Y10T29/49117 , Y10T29/49121 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , Y10T29/49156 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.
摘要翻译：一种用于制造用于支撑与第二IC芯片串联连接的第一IC芯片的IC支架的方法; 所述IC支架包括一组交替的铜特征层和绝缘环绕的通孔，所述第一IC管芯可粘合到所述IC支架上，并且所述第二IC管芯可在所述IC支架内部的空腔内接合，其中所述空腔由蚀刻铜基，并选择性地蚀刻掉铜层。

6. 发明授权

US5946600A Method for manufacturing an electronic structure 失效
标题翻译：电子结构的制造方法
公开(公告)号：US5946600A
公开(公告)日：1999-08-31
申请号：US835514
申请日：1997-04-08
申请人： Dror Hurwitz , Eva Igner , Boris Yofis , Dror Katz
发明人： Dror Hurwitz , Eva Igner , Boris Yofis , Dror Katz
IPC分类号： H01L21/48 , H01L21/768 , H01L23/532 , H01L23/538 , H05K3/46 , H01L21/44
CPC分类号： H05K3/4647 , H01L21/4846 , H01L21/4857 , H01L21/76885 , H01L23/53223 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L2224/32225 , H01L2224/45147 , H01L2224/48227 , H01L2224/48228 , H01L2224/48235 , H01L2224/73265 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H05K2203/0315 , H05K2203/1142
摘要： A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.
摘要翻译：一种用于制造电子互连结构的方法，该方法包括以下步骤：在具有至少一个暴露的铝表面的电介质材料表面上沉积粘附金属层; 在所述粘附金属层上沉积阻挡金属层; 在阻挡金属层上沉积第一层铝; 在第一层铝上沉积中间阻挡金属层; 在中间阻挡金属层的顶部上施加光致抗蚀剂层; 曝光和显影光致抗蚀剂层; 去除暴露的阻挡金属和光致抗蚀剂层，在铝层上留下一层阻挡金属; 通过多孔阳极氧化将未被阻挡金属覆盖的铝层的那些部分转化成多孔氧化铝; 去除多孔氧化铝; 并且去除暴露的阻挡金属和粘合金属层以留下暴露的图案化铝，以及通过该方法制造的电子互连结构。

7. 发明授权

US06262376B1 Chip carrier substrate 有权
标题翻译：芯片载体衬底
公开(公告)号：US06262376B1
公开(公告)日：2001-07-17
申请号：US09372601
申请日：1999-08-12
申请人： Dror Hurwitz , Boris Yofis , Dror Katz , Eva Igner
发明人： Dror Hurwitz , Boris Yofis , Dror Katz , Eva Igner
IPC分类号： H05K103
CPC分类号： H05K3/4647 , H01L21/4846 , H01L21/4857 , H01L23/498 , H01L23/49822 , H01L2924/0002 , H01L2924/3011 , H05K2203/0315 , H05K2203/1142 , H01L2924/00
摘要： A chip carrier substrate including a lower layer and at least one upper layer of copper conductors on a base, a plurality of aluminum studs formed by anodization to be of substantially identical height which interconnect the layers of conductors, a layer of barrier metal electrically connecting the aluminum studs and the copper conductors to prevent direct contact therebetween, the aluminum studs and at least the upper layer of copper conductor being surrounded by a polymeric dielectric material, and a layer of adhesion/barrier metal beneath the upper copper conductor layer, between the upper copper conductor layer and the dielectric material.
摘要翻译：一种芯片载体基板，包括下层和至少一层铜导体的基底上的多个铝螺柱，通过阳极氧化形成的具有基本上相同的高度的多个铝螺柱，其互连导体层，一层阻挡金属电连接铝螺柱和铜导体，以防止它们之间的直接接触，铝螺柱和至少铜导体的上层被聚合物电介质材料包围，并且在上部铜导体层下面的上部铜导体层之间的粘附/阻挡金属层铜导体层和电介质材料。

8. 发明授权

US06280640B1 Process for manufacturing a chip carrier substrate 有权
标题翻译：芯片载体基板的制造方法
公开(公告)号：US06280640B1
公开(公告)日：2001-08-28
申请号：US09303422
申请日：1999-05-03
申请人： Dror Hurwitz , Boris Yofis , Dror Katz , Eva Igner
发明人： Dror Hurwitz , Boris Yofis , Dror Katz , Eva Igner
IPC分类号： H01B1300
CPC分类号： H05K3/4647 , H01L21/4846 , H01L21/4857 , H01L23/498 , H01L23/49822 , H01L2924/0002 , H01L2924/3011 , H05K2203/0315 , H05K2203/1142 , H01L2924/00
摘要： A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.
摘要翻译：一种制造芯片载体衬底的方法，该方法包括以下步骤：在衬底上提供第一铜导体层，在第一层铜导体上形成第一层阻挡金属层，在第一层上形成一层铝层的阻挡金属，在铝层上形成第二阻挡金属，将顶部阻挡金属图案化成螺柱形式，阳极氧化未被顶部阻挡金属保护的铝，去除氧化铝并图案化第一铜层，去除所有暴露的阻隔金属; 用聚合物电介质围绕螺栓和铜导体; 抛光聚合物电介质以暴露螺柱; 以及在所述平面聚合物电介质上形成第二层铜导体。

9. 发明授权

US06262478B1 Electronic interconnect structure and method for manufacturing it 有权
标题翻译：电子互连结构及其制造方法
公开(公告)号：US06262478B1
公开(公告)日：2001-07-17
申请号：US09310328
申请日：1999-05-12
申请人： Dror Hurwitz , Eva Igner , Boris Yofis , Dror Katz
发明人： Dror Hurwitz , Eva Igner , Boris Yofis , Dror Katz
IPC分类号： H01L23053
CPC分类号： H01L21/76885 , H01L23/53223 , H01L23/5329 , H01L23/5383 , H01L23/5384 , H01L24/48 , H01L2224/05599 , H01L2224/32225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48235 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/09701 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.
摘要翻译：一种用于制造电子互连结构的方法，该方法包括以下步骤：在具有至少一个暴露的铝表面的电介质材料表面上沉积粘附金属层; 在所述粘附金属层上沉积阻挡金属层; 在阻挡金属层上沉积第一层铝; 在第一层铝上沉积中间阻挡金属层; 在中间阻挡金属层的顶部上施加光致抗蚀剂层; 曝光和显影光致抗蚀剂层; 去除暴露的阻挡金属和光致抗蚀剂层，在铝层上留下一层阻挡金属; 通过多孔阳极氧化将未被阻挡金属覆盖的铝层的那些部分转化成多孔氧化铝; 去除多孔氧化铝; 并且去除暴露的阻挡金属和粘合金属层以留下暴露的图案化铝，以及通过该方法制造的电子互连结构。

10. 发明授权

US10466572B2 Method of fabrication for single crystal piezoelectric RF resonators and filters 有权
公开(公告)号：US10466572B2
公开(公告)日：2019-11-05
申请号：US15679879
申请日：2017-08-17
申请人： Dror Hurwitz
发明人： Dror Hurwitz
IPC分类号： G02F1/35 , G02F1/39 , H03H9/56 , H03H9/02 , H03H3/02 , H01S3/00 , H03B17/00
摘要： 1. A method of fabricating an RF filter comprising an array of resonators comprising the steps of: Obtaining a removable carrier with release layer; Growing a piezoelectric film on a removable carrier; Applying a first electrode to the piezoelectric film; Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; Attaching the backing membrane to the first electrode; Detaching the removable carrier; Measuring and trimming the piezoelectric film as necessary; Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; Etching down through coatings and backing membrane to a silicon dioxide layer between the backing membrane and the cover to form trenches; Applying a passivation layer into the trenches and around the piezoelectric islands; Depositing a second electrode layer over the piezoelectric film islands and surrounding passivation layer; Applying connections for subsequent electrical coupling to an interposer; Selectively removing second electrode material leaving coupled resonator arrays; Creating a gasket around perimeter of the resonator array; Thinning down cover to desired thickness; Optionally fabricating upper cavities between the backing membrane and cover by drilling holes through the cover and then selectively etching away the silicon dioxide; Dicing the wafer into flip chip single unit filter arrays; Obtaining an interposer; Optionally applying a dam to the interposer surface to halt overfill flow; Coupling the flip chip single unit filter array to pads of the interposer by reflow of the solder cap; Encapsulating with polymer underfill/overfill; and Singulating into separate filter modules, wherein wherein the piezoelectric layer comprises a mixed AlN single crystal layer a c-axis orientation.

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