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1. 发明申请

US20080150082A1 POWER TRANSISTOR FEATURING A DOUBLE-SIDED FEED DESIGN AND METHOD OF MAKING THE SAME 有权
标题翻译：功率晶体管具有双面进料设计及其制造方法
公开(公告)号：US20080150082A1
公开(公告)日：2008-06-26
申请号：US11671035
申请日：2007-02-05
申请人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
发明人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
IPC分类号： H01L27/082
CPC分类号： H01L29/73 , H01L23/4824 , H01L24/13 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/7322 , H01L2224/16 , H01L2924/19043 , H01L2924/30107
摘要： A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions. The base contact configuration includes (i) a first base feed (150) coupled to the base portion of each unit cell device via a first end of at least one base finger (154) associated with a corresponding unit cell device and (ii) a second base feed (152) coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device. The emitter contact configuration includes (i) a first emitter feed (172) coupled to the emitter portion of each unit cell device via a first end of an emitter metallization (176) associated with a corresponding unit cell device and (ii) a second emitter feed (174) coupled to the emitter portion of each unit cell device via an opposite end of the emitter metallization associated with the corresponding unit cell device. The collector contact configuration includes a collector feed (188) coupled to the collector portion of each unit cell device.
摘要翻译：功率晶体管（210）包括多个单位电池器件（212），基极触点配置，发射极触点配置和集电极触点配置。多个单电池器件沿轴线（194）布置，每个单元电池器件包括基极（80），发射极（82）和集电极（84）部分。基本接触配置包括：（i）经由与相应的单位电池器件相关联的至少一个基本手指（154）的第一端耦合到每个单元电池器件的基座部分的第一基本馈电（150）和（ii）第二基本馈送（152），其经由与所述对应的单元设备相关联的所述至少一个基本指的相对端耦合到每个单元单元设备的基本部分。发射极接触配置包括：（i）经由与相应的单位电池器件相关联的发射极金属化（176）的第一端耦合到每个单位电池器件的发射极部分的第一发射极馈电（172）和（ii）第二发射极馈电（174）经由与相应的单位电池器件相关联的发射极金属化的相对端耦合到每个单位电池器件的发射极部分。集电极接触配置包括耦合到每个单位电池器件的集电极部分的集电极馈送（188）。

2. 发明授权

US07821102B2 Power transistor featuring a double-sided feed design and method of making the same 有权
标题翻译：功率晶体管采用双面进料设计和制作方法
公开(公告)号：US07821102B2
公开(公告)日：2010-10-26
申请号：US11671035
申请日：2007-02-05
申请人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
发明人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
IPC分类号： H01L27/082 , H01L29/70
CPC分类号： H01L29/73 , H01L23/4824 , H01L24/13 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/7322 , H01L2224/16 , H01L2924/19043 , H01L2924/30107
摘要： A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions. The base contact configuration includes (i) a first base feed (150) coupled to the base portion of each unit cell device via a first end of at least one base finger (154) associated with a corresponding unit cell device and (ii) a second base feed (152) coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device. The emitter contact configuration includes (i) a first emitter feed (172) coupled to the emitter portion of each unit cell device via a first end of an emitter metallization (176) associated with a corresponding unit cell device and (ii) a second emitter feed (174) coupled to the emitter portion of each unit cell device via an opposite end of the emitter metallization associated with the corresponding unit cell device. The collector contact configuration includes a collector feed (188) coupled to the collector portion of each unit cell device.
摘要翻译：功率晶体管（210）包括多个单位电池器件（212），基极触点配置，发射极触点配置和集电极触点配置。多个单电池器件沿轴线（194）布置，每个单元电池器件包括基极（80），发射极（82）和集电极（84）部分。基本接触配置包括：（i）经由与相应的单位电池器件相关联的至少一个基本手指（154）的第一端耦合到每个单元电池器件的基座部分的第一基本馈电（150）和（ii）第二基本馈送（152），其经由与所述对应的单元设备相关联的所述至少一个基本指的相对端耦合到每个单元单元设备的基本部分。发射极接触配置包括：（i）经由与相应的单位电池器件相关联的发射极金属化（176）的第一端耦合到每个单位电池器件的发射极部分的第一发射极馈电（172）和（ii）第二发射极馈电（174）经由与相应的单位电池器件相关联的发射极金属化的相对端耦合到每个单位电池器件的发射极部分。集电极接触配置包括耦合到每个单位电池器件的集电极部分的集电极馈送（188）。

3. 发明申请

US20110241159A1 HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE 有权
标题翻译：具有降低PARASIIC电容的高效放大器
公开(公告)号：US20110241159A1
公开(公告)日：2011-10-06
申请号：US13159635
申请日：2011-06-14
申请人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
发明人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
IPC分类号： H01L23/58
CPC分类号： H01L29/735 , H01L21/8222 , H01L27/082 , H01L29/10 , H03F1/083
摘要： A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
摘要翻译：提供了一种半导体放大器，包括：衬底和形成在衬底上的一个或多个单元放大单元（UAC），其中每个UAC由至少延伸至衬底的第一侧向电介质填充沟槽（DFT）隔离壁和多个 UAC被第一隔离壁外部的类似深度的第二横向DFT隔离壁围绕，并且当两个或多个单元电池存在时和/或位于第一和第二隔离壁之间时，位于第一隔离壁之间的另外的半导体区域，相对于衬底电浮动。这降低了放大单元的寄生电容并提高了功率附加效率。通过在衬底和掩埋层触点之间提供中间掺杂的另一半导体层来避免使用高电阻率衬底时掩埋层触点之间的过度泄漏。

4. 发明授权

US08546908B2 High efficiency amplifier with reduced parasitic capacitance 有权
标题翻译：具有降低寄生电容的高效放大器
公开(公告)号：US08546908B2
公开(公告)日：2013-10-01
申请号：US13159635
申请日：2011-06-14
申请人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
发明人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L21/8222 , H01L27/082 , H01L29/10 , H03F1/083
摘要： A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
摘要翻译：提供了一种半导体放大器，包括：衬底和形成在衬底上的一个或多个单元放大单元（UAC），其中每个UAC由至少延伸至衬底的第一侧向电介质填充沟槽（DFT）隔离壁和多个 UAC被第一隔离壁外部的类似深度的第二横向DFT隔离壁围绕，并且当两个或多个单元电池存在时和/或位于第一和第二隔离壁之间时，位于第一隔离壁之间的另外的半导体区域，相对于衬底电浮动。这降低了放大单元的寄生电容并提高了功率附加效率。通过在衬底和掩埋层触点之间提供中间掺杂的另一半导体层来避免使用高电阻率衬底时掩埋层触点之间的过度泄漏。

5. 发明授权

US07982282B2 High efficiency amplifier with reduced parasitic capacitance 有权
标题翻译：具有降低寄生电容的高效放大器
公开(公告)号：US07982282B2
公开(公告)日：2011-07-19
申请号：US12109798
申请日：2008-04-25
申请人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
发明人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L21/8222 , H01L27/082 , H01L29/10 , H03F1/083
摘要： A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
摘要翻译：提供了一种半导体放大器，包括：衬底和形成在衬底上的一个或多个单元放大单元（UAC），其中每个UAC由至少延伸至衬底的第一侧向电介质填充沟槽（DFT）隔离壁和多个 UAC被第一隔离壁外部的类似深度的第二横向DFT隔离壁围绕，并且当两个或多个单元电池存在时和/或位于第一和第二隔离壁之间时，位于第一隔离壁之间的另外的半导体区域，相对于衬底电浮动。这降低了放大单元的寄生电容并提高了功率附加效率。通过在衬底和掩埋层触点之间提供中间掺杂的另一半导体层来避免使用高电阻率衬底时掩埋层触点之间的过度泄漏。

6. 发明申请

US20090267689A1 HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE 有权
标题翻译：具有降低PARASIIC电容的高效放大器
公开(公告)号：US20090267689A1
公开(公告)日：2009-10-29
申请号：US12109798
申请日：2008-04-25
申请人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel E. Keys , Sandra J. Wipf , Evan F. Yu
发明人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel E. Keys , Sandra J. Wipf , Evan F. Yu
IPC分类号： H03F3/04 , H01L27/12 , H01L21/331
CPC分类号： H01L29/735 , H01L21/8222 , H01L27/082 , H01L29/10 , H03F1/083
摘要： A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
摘要翻译：提供了一种半导体放大器，包括：衬底和形成在衬底上的一个或多个单元放大单元（UAC），其中每个UAC由至少延伸至衬底的第一侧向电介质填充沟槽（DFT）隔离壁和多个 UAC被第一隔离壁外部的类似深度的第二横向DFT隔离壁围绕，并且当两个或多个单元电池存在时和/或位于第一和第二隔离壁之间时，位于第一隔离壁之间的另外的半导体区域，相对于衬底电浮动。这降低了放大单元的寄生电容并提高了功率附加效率。通过在衬底和掩埋层触点之间提供中间掺杂的另一半导体层来避免使用高电阻率衬底时掩埋层触点之间的过度泄漏。

7. 发明授权

US5837590A Isolated vertical PNP transistor without required buried layer 失效
标题翻译：隔离垂直PNP晶体管，无需埋层
公开(公告)号：US5837590A
公开(公告)日：1998-11-17
申请号：US869646
申请日：1997-06-05
申请人： Lawrence F. Latham , Theresa M. Keller
发明人： Lawrence F. Latham , Theresa M. Keller
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/7322
摘要： A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conductivity in the P- surface layer (12) contains a collector region (25) of P- type conductivity. A base region (30) of N type conductivity is contained in the collector region (25), and an emitter region (40) of P+ type conductivity is contained in the base region (30). The base region (30) may be provided with a higher N type impurity concentration than a P type impurity concentration of the collector region (25). At least the collector region (25) and the base region (30) may be self aligned. The collector region (25) may be of thickness of about 2.2 .mu.m, the base region (30) of thickness of about 0.1 .mu.m, and the emitter region (40) of thickness of about 0.4 .mu.m. Although the transistor is vertically constructed, base and collector contacts (60 and 42-43) may be provided at a surface of the surface layer (12) opposite the substrate (11). A contact (62) may also be provided for the isolation layer (14) at the surface.
摘要翻译：一种垂直PNP晶体管及其方法，用于在P +型导电性基板（11）的表面上提供一种在可能为外延层的表面层（12）中具有P-型导电性的晶体管。在P-表面层（12）中具有N-型导电性的隔离区域（14）包含P-型导电性的集电极区域（25）。在集电极区域（25）中包含N型导电性的基极区域（30），并且在基极区域（30）中包含P +型导电性的发射极区域（40）。基极区域（30）可以具有比集电极区域（25）的P型杂质浓度高的N型杂质浓度。至少集电极区域（25）和基极区域（30）可以是自对准的。集电极区域（25）可以具有约2.2μm的厚度，厚度约0.1μm的基极区域（30）和厚度约0.4μm的发射极区域（40）。虽然晶体管是垂直构造的，但是可以在与衬底（11）相对的表面层（12）的表面处提供基极和集电极触点（60和42-43）。还可以在表面处为隔离层（14）提供接触（62）。

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