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1. 发明申请

US20110241159A1 HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE 有权
标题翻译：具有降低PARASIIC电容的高效放大器
公开(公告)号：US20110241159A1
公开(公告)日：2011-10-06
申请号：US13159635
申请日：2011-06-14
申请人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
发明人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
IPC分类号： H01L23/58
CPC分类号： H01L29/735 , H01L21/8222 , H01L27/082 , H01L29/10 , H03F1/083
摘要： A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
摘要翻译：提供了一种半导体放大器，包括：衬底和形成在衬底上的一个或多个单元放大单元（UAC），其中每个UAC由至少延伸至衬底的第一侧向电介质填充沟槽（DFT）隔离壁和多个 UAC被第一隔离壁外部的类似深度的第二横向DFT隔离壁围绕，并且当两个或多个单元电池存在时和/或位于第一和第二隔离壁之间时，位于第一隔离壁之间的另外的半导体区域，相对于衬底电浮动。这降低了放大单元的寄生电容并提高了功率附加效率。通过在衬底和掩埋层触点之间提供中间掺杂的另一半导体层来避免使用高电阻率衬底时掩埋层触点之间的过度泄漏。

2. 发明授权

US08546908B2 High efficiency amplifier with reduced parasitic capacitance 有权
标题翻译：具有降低寄生电容的高效放大器
公开(公告)号：US08546908B2
公开(公告)日：2013-10-01
申请号：US13159635
申请日：2011-06-14
申请人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
发明人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L21/8222 , H01L27/082 , H01L29/10 , H03F1/083
摘要： A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
摘要翻译：提供了一种半导体放大器，包括：衬底和形成在衬底上的一个或多个单元放大单元（UAC），其中每个UAC由至少延伸至衬底的第一侧向电介质填充沟槽（DFT）隔离壁和多个 UAC被第一隔离壁外部的类似深度的第二横向DFT隔离壁围绕，并且当两个或多个单元电池存在时和/或位于第一和第二隔离壁之间时，位于第一隔离壁之间的另外的半导体区域，相对于衬底电浮动。这降低了放大单元的寄生电容并提高了功率附加效率。通过在衬底和掩埋层触点之间提供中间掺杂的另一半导体层来避免使用高电阻率衬底时掩埋层触点之间的过度泄漏。

3. 发明授权

US07982282B2 High efficiency amplifier with reduced parasitic capacitance 有权
标题翻译：具有降低寄生电容的高效放大器
公开(公告)号：US07982282B2
公开(公告)日：2011-07-19
申请号：US12109798
申请日：2008-04-25
申请人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
发明人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel M. Keys , Sandra J. Wipf , Evan F. Yu
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L21/8222 , H01L27/082 , H01L29/10 , H03F1/083
摘要： A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
摘要翻译：提供了一种半导体放大器，包括：衬底和形成在衬底上的一个或多个单元放大单元（UAC），其中每个UAC由至少延伸至衬底的第一侧向电介质填充沟槽（DFT）隔离壁和多个 UAC被第一隔离壁外部的类似深度的第二横向DFT隔离壁围绕，并且当两个或多个单元电池存在时和/或位于第一和第二隔离壁之间时，位于第一隔离壁之间的另外的半导体区域，相对于衬底电浮动。这降低了放大单元的寄生电容并提高了功率附加效率。通过在衬底和掩埋层触点之间提供中间掺杂的另一半导体层来避免使用高电阻率衬底时掩埋层触点之间的过度泄漏。

4. 发明申请

US20090267689A1 HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE 有权
标题翻译：具有降低PARASIIC电容的高效放大器
公开(公告)号：US20090267689A1
公开(公告)日：2009-10-29
申请号：US12109798
申请日：2008-04-25
申请人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel E. Keys , Sandra J. Wipf , Evan F. Yu
发明人： Dragan Zupac , Brian D. Griesbach , Theresa M. Keller , Joel E. Keys , Sandra J. Wipf , Evan F. Yu
IPC分类号： H03F3/04 , H01L27/12 , H01L21/331
CPC分类号： H01L29/735 , H01L21/8222 , H01L27/082 , H01L29/10 , H03F1/083
摘要： A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
摘要翻译：提供了一种半导体放大器，包括：衬底和形成在衬底上的一个或多个单元放大单元（UAC），其中每个UAC由至少延伸至衬底的第一侧向电介质填充沟槽（DFT）隔离壁和多个 UAC被第一隔离壁外部的类似深度的第二横向DFT隔离壁围绕，并且当两个或多个单元电池存在时和/或位于第一和第二隔离壁之间时，位于第一隔离壁之间的另外的半导体区域，相对于衬底电浮动。这降低了放大单元的寄生电容并提高了功率附加效率。通过在衬底和掩埋层触点之间提供中间掺杂的另一半导体层来避免使用高电阻率衬底时掩埋层触点之间的过度泄漏。

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