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1. 发明授权

US07279856B1 Environmental and health monitoring circuitry for storage processor I/O annex module 有权
标题翻译：用于存储处理器I / O附件模块的环境和健康监测电路
公开(公告)号：US07279856B1
公开(公告)日：2007-10-09
申请号：US11395460
申请日：2006-03-31
申请人： Douglas Sullivan , Stephen Strickland , Michael J. Kozel
发明人： Douglas Sullivan , Stephen Strickland , Michael J. Kozel
IPC分类号： H02P7/08
CPC分类号： H05K7/20727 , H05K7/20836 , Y10T307/615
摘要： A hot-pluggable I/O annex module of a storage processor assembly includes interface circuitry providing connections to an optional I/O interface module. The I/O annex module includes redundant cooling fans providing cooling airflow to an I/O annex mounting area, main power conversion circuitry for generating main operating power for the interface circuitry, auxiliary power conversion circuitry for generating auxiliary power, a controller for monitoring and controlling the operation of cooling fans; and monitoring circuitry powered by the auxiliary power for monitoring correct operation of the controller and, upon detecting incorrect operation, disabling the main power conversion circuitry. The monitoring circuitry includes a watchdog timer and a latch collectively operative to (i) determine if a controller status signal indicating correct operation of the controller does not toggle for a watch interval, and if so then (ii) enter an operating state in which the main power conversion circuitry is disabled and cannot be re-enabled except by cycling the primary power or removing and reinserting the I/O annex module to/from the storage processor assembly.
摘要翻译：存储处理器组件的热插拔I / O附件模块包括提供到可选I / O接口模块的连接的接口电路。 I / O附件模块包括为I / O附件安装区域提供冷却气流的冗余冷却风扇，用于为接口电路产生主要工作功率的主电力转换电路，用于产生辅助电力的辅助电力转换电路，用于监视和控制冷却风扇的运行; 以及由辅助电源供电的监视电路，用于监视控制器的正确操作，并且在检测到不正确的操作时禁用主电力转换电路。监视电路包括看门狗定时器和锁存器，其共同操作以（i）确定指示控制器的正确操作的控制器状态信号是否在观看间隔内不切换，并且如果是，则（ii）进入操作状态，其中主电源转换电路被禁用，除了重新启动主电源或将I / O附件模块卸下并重新插入存储处理器组件外，无法重新启用。

2. 发明申请

US20070234136A1 Method and apparatus for detecting the presence of errors in data transmitted between components in a data storage system using an I2C protocol 有权
标题翻译：用于检测在使用I2C协议的数据存储系统中在组件之间传输的数据中存在错误的方法和装置
公开(公告)号：US20070234136A1
公开(公告)日：2007-10-04
申请号：US11394919
申请日：2006-03-31
申请人： Phillip Leef , Douglas Sullivan , Stephen Strickland , Alex Sanville
发明人： Phillip Leef , Douglas Sullivan , Stephen Strickland , Alex Sanville
IPC分类号： G06F11/00
CPC分类号： H04L1/0061 , H04L1/16 , H04L2001/0094
摘要： A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage processor. The controller further maintains a set of registers that store information associated with the data storage system and allows the storage processor to access the register via an I2C bus. The system utilizes an error detection procedure to allow detection of errors in the data transmitted between the controller and the storage processor. During operation, a checksum value is transmitted between the controller and the storage processor using the I2C bus during a register write or read procedure. The controller and the storage processor utilize the checksum value in an error detection procedure to detect the data errors resulting in transmission of the data by the I2C bus.
摘要翻译：数据存储系统包括存储处理器，其被配置为代表外部设备对存储阵列执行加载和存储操作。数据存储系统还包括控制器，其通过存储处理器耦合到存储阵列时隔离外部设备之间的通信。控制器还保持一组寄存器，其存储与数据存储系统相关联的信息，并允许存储处理器经由I2C总线访问寄存器。系统利用错误检测程序来检测在控制器和存储处理器之间传输的数据中的错误。在运行期间，在寄存器写入或读取过程期间，使用I2C总线在控制器和存储处理器之间传输校验和值。控制器和存储处理器利用错误检测过程中的校验和值来检测由I2C总线传输数据的数据错误。

3. 发明授权

US07502992B2 Method and apparatus for detecting presence of errors in data transmitted between components in a data storage system using an I2C protocol 有权
标题翻译：用于检测在使用I2C协议的数据存储系统中在组件之间传输的数据中存在错误的方法和装置
公开(公告)号：US07502992B2
公开(公告)日：2009-03-10
申请号：US11394919
申请日：2006-03-31
申请人： Phillip Leef , Douglas Sullivan , Stephen Strickland , Alex Sanville
发明人： Phillip Leef , Douglas Sullivan , Stephen Strickland , Alex Sanville
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： H04L1/0061 , H04L1/16 , H04L2001/0094
摘要： A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage processor. The controller further maintains a set of registers that store information associated with the data storage system and allows the storage processor to access the register via an I2C bus. The system utilizes an error detection procedure to allow detection of errors in the data transmitted between the controller and the storage processor. During operation, a checksum value is transmitted between the controller and the storage processor using the I2C bus during a register write or read procedure. The controller and the storage processor utilize the checksum value in an error detection procedure to detect the data errors resulting in transmission of the data by the I2C bus.
摘要翻译：数据存储系统包括存储处理器，其被配置为代表外部设备对存储阵列执行加载和存储操作。数据存储系统还包括控制器，其通过存储处理器耦合到存储阵列时隔离外部设备之间的通信。控制器还保持一组寄存器，其存储与数据存储系统相关联的信息，并允许存储处理器经由I2C总线访问寄存器。系统利用错误检测程序来检测在控制器和存储处理器之间传输的数据中的错误。在运行期间，在寄存器写入或读取过程期间，使用I2C总线在控制器和存储处理器之间传输校验和值。控制器和存储处理器利用错误检测过程中的校验和值来检测由I2C总线传输数据的数据错误。

4. 发明授权

US08031722B1 Techniques for controlling a network switch of a data storage system 有权
标题翻译：用于控制数据存储系统的网络交换机的技术
公开(公告)号：US08031722B1
公开(公告)日：2011-10-04
申请号：US12059127
申请日：2008-03-31
申请人： Alex Sanville , Douglas Sullivan , Stephen Strickland
发明人： Alex Sanville , Douglas Sullivan , Stephen Strickland
IPC分类号： H04L12/28 , H04L12/16
CPC分类号： H04L12/413 , H04L49/50 , H04L67/1097
摘要： A technique controls a network switch having a set of ports. The technique involves configuring the network switch to provide an initial set of communications paths between the ports. The initial set of communications paths defines an initial communications path topology within the network switch. The technique further involves receiving a configuration command which identifies a particular operating mode of the data storage system after configuring the network switch to provide the initial set of communications paths within the network switch. The technique further involves reconfiguring the network switch to provide a new set of communications paths between the ports in response to the configuration command. The new set of communications paths (i) defines a new communications path topology within the network switch, the new communications path topology being different than the initial communications path topology, and (ii) supports the particular operating mode of the data storage system.
摘要翻译：一种技术控制具有一组端口的网络交换机。该技术涉及配置网络交换机以提供端口之间的初始通信路径集合。初始的通信路径集定义了网络交换机内的初始通信路径拓扑。该技术还涉及在配置网络交换机以在网络交换机内提供初始通信路径集合的情况下，接收识别数据存储系统的特定操作模式的配置命令。该技术还涉及重新配置网络交换机以响应配置命令在端口之间提供新的一组通信路径。新的通信路径集（i）定义了网络交换机内新的通信路径拓扑，新的通信路径拓扑与初始通信路径拓扑不同，（ii）支持数据存储系统的特定操作模式。

5. 发明授权

US07380043B1 Method and apparatus for arbitrating for serial bus access 有权
标题翻译：用于仲裁串行总线访问的方法和装置
公开(公告)号：US07380043B1
公开(公告)日：2008-05-27
申请号：US10771811
申请日：2004-02-04
申请人： Bernard Warnakulasooriya , Steven Sardella , Mickey Felton , Stephen Strickland , Philip Roux
发明人： Bernard Warnakulasooriya , Steven Sardella , Mickey Felton , Stephen Strickland , Philip Roux
IPC分类号： G06F13/36
CPC分类号： G06F13/409 , G06F1/206 , G06F1/26 , G06F11/0757 , G06F11/2005 , G06F11/2015
摘要： In a highly available storage system, an enclosure includes first and second power supplies, and first and second controller boards. Each of the first and second controller boards includes first and second serial bus controllers. First and second serial buses are coupled to both of the first and second serial bus controllers on each of the first and second controller boards. The first serial bus is coupled to the first power supply, while the second serial bus coupled to the second power supply. The first and second serial buses are used for exchanging enclosure management and environmental information between the first and second power supplies and the first and second controller boards. The first and second serial buses are coupled to isolation switches so that redundant modules can operate if a serial bus controller fails.
摘要翻译：在高度可用的存储系统中，机箱包括第一和第二电源以及第一和第二控制器板。第一和第二控制器板中的每一个包括第一和第二串行总线控制器。第一和第二串行总线在第一和第二控制器板中的每一个上耦合到第一和第二串行总线控制器两者。第一串行总线耦合到第一电源，而第二串行总线耦合到第二电源。第一和第二串行总线用于在第一和第二电源以及第一和第二控制器板之间交换外壳管理和环境信息。第一和第二串行总线耦合到隔离开关，以便在串行总线控制器发生故障时冗余模块可以工作。

6. 发明授权

US07281150B1 Methods and apparatus for controlling operation of a data storage system 有权
标题翻译：用于控制数据存储系统的操作的方法和装置
公开(公告)号：US07281150B1
公开(公告)日：2007-10-09
申请号：US10810431
申请日：2004-03-26
申请人： Stephen Strickland
发明人： Stephen Strickland
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A data storage system includes power circuitry configured to provide power signals, storage processing circuitry configured to perform data storage operations, and a packaged microcontroller coupled to the power circuitry and the storage processing circuitry. The packaged microcontroller has input lines, output lines, and control circuitry coupled to the input lines and the output lines. The control circuitry is configured to (i) receive, on the input lines, first power signals (e.g., voltage signals for I/O circuitry) which is provided by the power circuitry to the storage processing circuitry, (ii) wait a predetermined time period in response to receipt of the first power signals on the input lines, and (iii) output, through the output lines, enable signals to the power circuitry after waiting the predetermined time period. The enable signals directs the power circuitry to provide second power signals to the storage processing circuitry (e.g., voltage signals for core circuitry).
摘要翻译：数据存储系统包括被配置为提供功率信号的电力电路，以及被配置为执行数据存储操作的存储处理电路，以及耦合到电源电路和存储处理电路的封装微控制器。封装的微控制器具有耦合到输入线和输出线的输入线，输出线和控制电路。控制电路被配置为（i）在输入线上接收由电源电路提供给存储处理电路的第一功率信号（例如，用于I / O电路的电压信号），（ii）等待预定时间响应于在输入线路上接收到第一电力信号的响应时间，以及（iii）通过输出线路在等待预定时间段之后向电力电路输出信号。使能信号指示电源电路向存储处理电路提供第二功率信号（例如，用于核心电路的电压信号）。

7. 发明授权

US07590776B1 Data storage techniques utilizing host-side multiplexers 有权
标题翻译：利用主机侧多路复用器的数据存储技术
公开(公告)号：US07590776B1
公开(公告)日：2009-09-15
申请号：US10746317
申请日：2003-12-24
申请人： John V. Burroughs , Stephen Strickland , Bassem N. Bishay
发明人： John V. Burroughs , Stephen Strickland , Bassem N. Bishay
IPC分类号： G06F3/00 , H04L12/66 , H04J3/26
CPC分类号： G06F3/0658 , G06F3/0613 , G06F3/0689 , G06F13/4022
摘要： A data storage system has a circuit board module, a set of Serial ATA devices, and a set of Serial ATA cables connecting the circuit board module to the set of Serial ATA devices. The circuit board module includes a circuit board, multiple host circuits mounted to the circuit board and multiplexer circuitry mounted to the circuit board. Each host circuit is configured to perform data storage operations on the behalf of an external client. The multiplexer circuitry is configured to (i) receive control signals from the host circuits and (ii) provide communications pathways between the host circuits and the set of Serial ATA devices in response to the control signals. Such an embodiment alleviates the need for multiple versions of disk drive assemblies and their associated costs.
摘要翻译：数据存储系统具有电路板模块，一组串行ATA设备和一组串行ATA电缆，将电路板模块连接到串行ATA设备。电路板模块包括电路板，安装到电路板的多个主机电路和安装到电路板的多路复用器电路。每个主机电路被配置为代表外部客户端执行数据存储操作。多路复用器电路被配置为（i）从主机电路接收控制信号，以及（ii）响应于控制信号，在主机电路和串行ATA设备组之间提供通信路径。这样的实施例减轻了对多个版本的磁盘驱动器组件及其相关成本的需求。

8. 发明授权

US07471512B1 Storage system assembly employing repeater amplifiers in I/O expansion module 有权
标题翻译：在I / O扩展模块中使用中继器放大器的存储系统组件
公开(公告)号：US07471512B1
公开(公告)日：2008-12-30
申请号：US11863550
申请日：2007-09-28
申请人： Stephen Strickland
发明人： Stephen Strickland
IPC分类号： H05K5/00 , H05K7/00 , G06F3/00 , G06F1/16
CPC分类号： G06F13/4068 , G06F3/0626 , G06F3/0658 , G06F3/0683
摘要： A storage system assembly includes a storage processor (SP) module and an input/output (I/O) expansion module disposed between an and opening of an enclosure and a midplane circuit board. The SP module includes (i) a storage processor, (ii) first I/O interface modules at the end opening, and (iii) circuit traces of high-speed serial data links, the circuit traces including first circuit traces interconnecting the storage processor with the first I/O interface modules, and second circuit traces interconnecting the storage processor with the circuit traces of the midplane. The I/O expansion module includes (i) second I/O interface modules at the end opening of the enclosure, (ii) a set of repeater amplifiers, and (iii) circuit traces of the high-speed serial data links, the circuit traces including third circuit traces interconnect the repeater amplifiers with the second I/O interface modules, and fourth circuit traces interconnect the repeater amplifiers with circuit traces of the midplane, such that the second, third and fourth circuit traces along with the circuit traces of the midplane interconnect the storage processor with the second I/O interface modules via the repeater amplifiers. The repeater amplifiers perform electrical regeneration of high-speed binary data signals between the third and fourth circuit traces.
摘要翻译：存储系统组件包括存储处理器（SP）模块和设置在外壳和中板面电路板的开口之间的输入/输出（I / O）扩展模块。 SP模块包括（i）存储处理器，（ii）端部开口处的第一I / O接口模块，以及（iii）高速串行数据链路的电路迹线，电路迹线包括互连存储处理器的第一电路迹线具有第一I / O接口模块和将存储处理器与中平面的电路迹线互连的第二电路迹线。 I / O扩展模块包括（i）机柜端部开口处的第二个I / O接口模块，（ii）一组中继器放大器，以及（iii）高速串行数据链路的电路走线，该电路包括第三电路迹线的迹线将中继器放大器与第二I / O接口模块互连，并且第四电路迹线将中继器放大器与中平面的电路迹线互连，使得第二，第三和第四电路跟踪电路迹线中间板通过中继器放大器将存储处理器与第二个I / O接口模块互连。中继器放大器在第三和第四电路迹线之间执行高速二进制数据信号的电再生。

9. 发明授权

US07293198B2 Techniques for maintaining operation of data storage system during a failure 有权
标题翻译：在故障期间保持数据存储系统的操作的技术
公开(公告)号：US07293198B2
公开(公告)日：2007-11-06
申请号：US10808839
申请日：2004-03-25
申请人： Stephen Strickland , John V. Burroughs , Timothy Dorr
发明人： Stephen Strickland , John V. Burroughs , Timothy Dorr
IPC分类号： G06F11/00
CPC分类号： G06F11/0727 , G06F11/0757 , G06F11/2089
摘要： A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit. The controller is configured to enable operation of the interfacing portion to provide communications between the first and second storage processors, sense a failure within the clock circuit, and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation. Such resetting of the interfacing portion prevents the remaining storage processor from locking up, thus freeing that storage processor so that it is capable of continuing to operate even after the failure.
摘要翻译：数据存储系统具有第一存储处理器，第二存储处理器和通信子系统。通信子系统具有（i）在第一存储处理器和第二存储处理器之间互连的接口部分，（ii）耦合到接口部分的时钟电路，以及（iii）耦合到接口部分和时钟电路的控制器。控制器被配置为使得接口部分的操作能够在第一和第二存储处理器之间提供通信，感测时钟电路内的故障，并且响应于感测到的故障来重置接口部分，以使第一和第二存储器处理器继续运行。接口部分的这种复位防止剩余的存储处理器锁定，从而释放该存储处理器，使得即使在故障之后它也能继续运行。

10. 发明授权

US08103801B1 Marking and faulting input/output ports of an electronics system 有权
标题翻译：电子系统的输入/输出端口的标记和故障
公开(公告)号：US08103801B1
公开(公告)日：2012-01-24
申请号：US11864115
申请日：2007-09-28
申请人： Steven D. Sardella , Stephen Strickland , Thomas N. Dibb
发明人： Steven D. Sardella , Stephen Strickland , Thomas N. Dibb
IPC分类号： G06F3/00
CPC分类号： G06F11/325
摘要： Described is an electronics system and method for marking and faulting I/O ports of an I/O module in the electronics system. Each I/O port has an associated light-emitting system that is capable of emitting a plurality of different colors. At least one color is blinked at a first rate to produce a first status indicator for the I/O port. Each color of the different colors is alternately blinked at a second rate to produce a second status indicator for the I/O port. One of the status indicators is for marking the I/O port and the other status indicator is for faulting the I/O port. In one embodiment, the light-emitting system includes a plurality of differently colored LEDs. In another embodiment, the light-emitting system includes only one multicolor LED. Various I/O technologies including Fiber Channel, Fiber Connectivity, Ethernet, serial attached SCSI, IPsec, Infiniband, and iSCSI, can implement marking and faulting.
摘要翻译：描述了用于在电子系统中标记和故障I / O模块的I / O端口的电子系统和方法。每个I / O端口具有能够发射多种不同颜色的相关联的发光系统。至少一种颜色以第一速率闪烁，以产生I / O端口的第一状态指示器。不同颜色的每种颜色以第二速率交替闪烁，以产生用于I / O端口的第二状态指示符。其中一个状态指示器是用于标记I / O端口，另一个状态指示灯用于使I / O端口发生故障。在一个实施例中，发光系统包括多个不同颜色的LED。在另一个实施例中，发光系统仅包括一个多色LED。各种I / O技术，包括光纤通道，光纤连接，以太网，串行连接SCSI，IPsec，Infiniband和iSCSI都可以实现标记和故障。

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