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1. 发明授权

US07217580B2 Method for processing an integrated circuit 有权
标题翻译：集成电路处理方法
公开(公告)号：US07217580B2
公开(公告)日：2007-05-15
申请号：US10973704
申请日：2004-10-26
申请人： Douglas S. Ondricek , David V. Pedersen
发明人： Douglas S. Ondricek , David V. Pedersen
IPC分类号： G01R31/66 , H01L21/66 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： G01R1/0466 , G01R1/0408 , G01R1/0433 , G01R31/01 , G01R31/2863 , G01R31/2867 , G01R31/2893 , H01L21/67294 , H01L23/04 , H01L23/13 , H01L23/32 , H01L23/5385 , H01L24/72 , H01L2223/54473 , H01L2224/16 , H01L2224/73251 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/16152 , H05K3/325 , H05K2201/09472 , H01L2924/00 , H01L2224/72
摘要： Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.
摘要翻译：用于处理包括集成电路的至少一个管芯的方法。在本发明的方法的一个示例中，将识别码应用于载体。单片模具沉积在保持单模模具的载体中。单片模具包括集成电路。可以在将分割的裸片沉积到载体中之前或之后将识别码应用于载体。载体可以用于测试单个模具，并且可以包括多个单个模具或仅一个单模模具。在本发明方法的另一个例子中，将识别码应用于管芯。模具沉积在保持模具的载体中。芯片包括集成电路，并且载体以单模形式保持模具。通常，模具被放置在载体中而没有任何可保护模具的包装。识别码可以在将其沉积到载体中之前或之后施加于该芯片。

2. 发明授权

US06627483B2 Method for mounting an electronic component 失效
标题翻译：电子部件的安装方法
公开(公告)号：US06627483B2
公开(公告)日：2003-09-30
申请号：US09260795
申请日：1999-03-01
申请人： Douglas S. Ondricek , David V. Pedersen
发明人： Douglas S. Ondricek , David V. Pedersen
IPC分类号： H01L2144
CPC分类号： G01R1/0466 , G01R1/0408 , G01R1/0433 , G01R31/01 , G01R31/2863 , G01R31/2867 , G01R31/2893 , H01L21/67294 , H01L23/04 , H01L23/13 , H01L23/32 , H01L23/5385 , H01L24/72 , H01L2223/54473 , H01L2224/16 , H01L2224/73251 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/16152 , H05K3/325 , H05K2201/09472 , H01L2924/00 , H01L2224/72
摘要： A method for mounting an electronic component. In one example of this method, the electronic component is an integrated circuit which is placed against an element of a carrier, such as a frame of a carrier. The electronic component has a plurality of elongate, resilient, electrical contact elements which are mounted on a corresponding first electrical contact pads on the electronic component. The electronic component is secured to the carrier, aNd the carrier is pressed against a first substrate having a plurality of second electrical contacts on a surface of the first substrate. In a typical example of this method, the electronic component is an integrated circuit which is being tested while being held in a carrier. The integrated circuit has been singulated from a wafer containing a plurality of integrated circuits.
摘要翻译：一种用于安装电子部件的方法。在该方法的一个示例中，电子部件是集成电路，其被放置在诸如载体的框架的载体的元件上。电子部件具有多个细长的，弹性的电接触元件，其安装在电子部件上相应的第一电接触焊盘上。电子部件被固定到载体上，一个载体被压靠在第一基板上，该第一基板在第一基板的表面上具有多个第二电触点。在该方法的典型示例中，电子部件是在被保持在载体中时被测试的集成电路。集成电路已经从包含多个集成电路的晶片分离出来。

3. 发明授权

US06644982B1 Method and apparatus for the transport and tracking of an electronic component 失效
标题翻译：用于运输和跟踪电子部件的方法和装置
公开(公告)号：US06644982B1
公开(公告)日：2003-11-11
申请号：US09260466
申请日：1999-03-01
申请人： Douglas S. Ondricek , David V. Pedersen
发明人： Douglas S. Ondricek , David V. Pedersen
IPC分类号： H01R1200
CPC分类号： G01R1/0466 , G01R1/0408 , G01R1/0433 , G01R31/01 , G01R31/2863 , G01R31/2867 , G01R31/2893 , H01L21/67294 , H01L23/04 , H01L23/13 , H01L23/32 , H01L23/5385 , H01L24/72 , H01L2223/54473 , H01L2224/16 , H01L2224/73251 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/16152 , H05K3/325 , H05K2201/09472 , H01L2924/00 , H01L2224/72
摘要： An apparatus for use in manipulating one or more IC die through testing after they have been cut from the original wafer. A carrier supports the die during the transport, testing, and/or final application. The die is placed into the carrier through an opening and then resides on a ledge lining some portion of the base of the opening. The spring components of the die extend downward through the opening and past the lower side of the ledge to allow for electrical contact. The die may be secured within the carrier opening in a variety of ways, including a cover coupled to the top of the carrier or through use of snap locks in the carrier. One useful cover has openings revealing a portion of the backside of the die. The cover openings allow access to the backside of the die. The carrier can be mounted onto a test bed for testing or a printed circuit board for a specific application. Alternatively, the carrier may first be positioned on the board with the die and the cover subsequently mounted thereon. Carrier standoffs for protection of leads and identification labels and marks for carrier and die may be used.
摘要翻译：一种用于在从原始晶片切割之后通过测试操纵一个或多个IC裸片的装置。载体在运输，测试和/或最终应用期间支撑模具。模具通过开口放置在载体中，然后驻留在开口的基部的一些部分上的凸缘上。模具的弹簧部件向下延伸穿过开口并经过凸缘的下侧以允许电接触。模具可以以各种方式固定在承载器开口内，包括联接到托架的顶部的盖或者通过使用托架中的卡锁。一个有用的盖具有露出模具背面的一部分的开口。盖开口允许进入模具的背面。载体可以安装在用于测试的试验台上或用于特定应用的印刷电路板。或者，载体可以首先在模具上定位在板上，并且盖随后安装在其上。可以使用用于保护引线和识别标签和载体和管芯的标记的载体对位。

4. 发明授权

US06887723B1 Method for processing an integrated circuit including placing dice into a carrier and testing 失效
标题翻译：一种用于处理集成电路的方法，包括将骰子放入载体并进行测试
公开(公告)号：US06887723B1
公开(公告)日：2005-05-03
申请号：US09260794
申请日：1999-03-01
申请人： Douglas S. Ondricek , David V. Pederson
发明人： Douglas S. Ondricek , David V. Pederson
IPC分类号： G01R1/04 , G01R31/01 , G01R31/28 , H01L23/04 , H01L23/13 , H01L23/32 , H01L23/48 , H01L23/538 , H05K3/32 , G01R31/26 , H01L21/18 , H01L21/44 , H01L21/50 , H01L21/66
CPC分类号： G01R1/0466 , G01R1/0408 , G01R1/0433 , G01R31/01 , G01R31/2863 , G01R31/2867 , G01R31/2893 , H01L21/67294 , H01L23/04 , H01L23/13 , H01L23/32 , H01L23/5385 , H01L24/72 , H01L2223/54473 , H01L2224/16 , H01L2224/73251 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/16152 , H05K3/325 , H05K2201/09472 , H01L2924/00 , H01L2224/72
摘要： Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.
摘要翻译：用于处理包括集成电路的至少一个管芯的方法。在本发明的方法的一个示例中，将识别码应用于载体。单片模具沉积在保持单模模具的载体中。单片模具包括集成电路。可以在将分割的裸片沉积到载体中之前或之后将识别码应用于载体。载体可以用于测试单个模具，并且可以包括多个单个模具或仅一个单模模具。在本发明方法的另一个例子中，将识别码应用于管芯。模具沉积在保持模具的载体中。芯片包括集成电路，并且载体以单模形式保持模具。通常，模具被放置在载体中而没有任何可保护模具的包装。识别码可以在将其沉积到载体中之前或之后施加于该芯片。

5. 发明授权

US08350191B2 Probe card thermal conditioning system 有权
标题翻译：探头卡热调节系统
公开(公告)号：US08350191B2
公开(公告)日：2013-01-08
申请号：US12267735
申请日：2008-11-10
申请人： Douglas S. Ondricek
发明人： Douglas S. Ondricek
IPC分类号： F24C7/10 , B65D85/00
CPC分类号： G01R31/2863 , G01R31/2874
摘要： Embodiments of apparatus for thermally conditioning probe cards prior to use in a testing system are provided herein. In some embodiments, a probe card thermal conditioning system may include an enclosure configured to support a probe card and a heat transfer element disposed proximate a bottom of the enclosure for thermally conditioning the probe card prior to installation in a prober. The heat transfer element may be a heating and/or cooling element. A controller may be provided for controlling operation of the heat transfer element, optionally with temperature feedback. Multiple enclosures may be provided for independently conditioning multiple probe cards. The enclosure may be contained in a cart or may be part of shipping container for shipping a probe card. A fan may be provided for circulating air within the enclosure. The fan may facilitate providing a dry purge gas to prevent condensate from forming on the probe card.
摘要翻译：本文提供了在测试系统中使用之前对探针卡进行热调节的设备的实施例。在一些实施例中，探针卡热调节系统可以包括被配置为支撑探针卡和设置在壳体的底部附近的传热元件的外壳，用于在探测器安装之前对探针卡进行热调节。传热元件可以是加热和/或冷却元件。可以提供用于控制传热元件的操作的控制器，任选地具有温度反馈。可以提供多个外壳以独立地调节多个探针卡。外壳可以包含在推车中，或者可以是用于运送探针卡的运输容器的一部分。可以提供用于在外壳内循环空气的风扇。风扇可以促进提供干净的吹扫气体，以防止在探针卡上形成冷凝物。

6. 发明授权

US6020749A Method and apparatus for performing testing of double-sided ball grid array devices 失效
标题翻译：用于执行双面球栅阵列器件测试的方法和装置
公开(公告)号：US6020749A
公开(公告)日：2000-02-01
申请号：US745531
申请日：1996-11-12
申请人： Terrel L. Morris , Douglas S. Ondricek
发明人： Terrel L. Morris , Douglas S. Ondricek
IPC分类号： G01R31/28 , G01R1/073 , G01R31/26 , H01L21/66 , G01R31/02
CPC分类号： G01R1/07378 , G01R31/2886
摘要： A system and method of constructing and using a test module in situations where internal access to test points on a substrate are unavailable because devices mounted on the substrate block physical access. The test module is itself a solderable substrate and is imposed, for testing purposes, between the main substrate and the mounted devices. For double-sided or stacked main boards, two or more such modules can be used interposed between the mounted devices and the main substrate. Vias in the module serve to make contact with the test points and to carry the signals to the edge of the module where cups can be formed by cutting the edge vias in half.
摘要翻译：在基板上测试点的内部访问不可用的情况下构建和使用测试模块的系统和方法，因为安装在基板上的设备阻止物理访问。测试模块本身是可焊接的基板，并且用于测试目的，在主基板和安装的装置之间施加。对于双面或堆叠的主板，可以在安装的装置和主基板之间插入两个或更多个这样的模块。模块中的通孔用于与测试点接触，并通过将边缘通孔切割成一半，将信号传送到模块的边缘，其中可以形成杯子。

7. 发明授权

US07977956B2 Method and apparatus for probe card alignment in a test system 有权
标题翻译：测试系统中探针卡校准的方法和设备
公开(公告)号：US07977956B2
公开(公告)日：2011-07-12
申请号：US12431271
申请日：2009-04-28
申请人： Keith J. Breinlinger , Benjamin N. Eldridge , Eric D. Hobbs , Douglas S. Ondricek
发明人： Keith J. Breinlinger , Benjamin N. Eldridge , Eric D. Hobbs , Douglas S. Ondricek
IPC分类号： G01R31/00 , G01R31/20
CPC分类号： G01R31/2891
摘要： Embodiments of methods and apparatus for aligning a probe card assembly in a test system are provided herein. In some embodiments, an apparatus for testing devices may include a probe card assembly having a plurality of probes, each probe having a tip for contacting a device to be tested, and having an identified set of one or more features that are preselected in accordance with selected criteria for aligning the probe card assembly within a prober after installation therein. In some embodiments, the identity of the identified set of one or more features may be communicated to the prober to facilitate a global alignment of the probe card assembly that minimizes an aggregate misalignment of all of the tips in the probe card assembly.
摘要翻译：本文提供了在测试系统中对准探针卡组件的方法和装置的实施例。在一些实施例中，用于测试装置的装置可以包括具有多个探针的探针卡组件，每个探针具有用于接触要测试的装置的尖端，并且具有根据本发明的预选的一组或多个特征在探针卡组件安装在其中之后将探针卡组件对准的选择标准。在一些实施例中，所识别的一个或多个特征集合的身份可以被传送到探测器，以促进探针卡组件的全局对准，其最小化探针卡组件中的所有尖端的聚集失准。

8. 发明申请

US20100271062A1 METHOD AND APPARATUS FOR PROBE CARD ALIGNMENT IN A TEST SYSTEM 有权
标题翻译：检测系统中探针卡对齐的方法与装置
公开(公告)号：US20100271062A1
公开(公告)日：2010-10-28
申请号：US12431271
申请日：2009-04-28
申请人： Keith J. Breinlinger , Benjamin N. Eldridge , Eric D. Hobbs , Douglas S. Ondricek
发明人： Keith J. Breinlinger , Benjamin N. Eldridge , Eric D. Hobbs , Douglas S. Ondricek
IPC分类号： G01R31/02
CPC分类号： G01R31/2891
摘要： Embodiments of methods and apparatus for aligning a probe card assembly in a test system are provided herein. In some embodiments, an apparatus for testing devices may include a probe card assembly having a plurality of probes, each probe having a tip for contacting a device to be tested, and having an identified set of one or more features that are preselected in accordance with selected criteria for aligning the probe card assembly within a prober after installation therein. In some embodiments, the identity of the identified set of one or more features may be communicated to the prober to facilitate a global alignment of the probe card assembly that minimizes an aggregate misalignment of all of the tips in the probe card assembly
摘要翻译：本文提供了在测试系统中对准探针卡组件的方法和装置的实施例。在一些实施例中，用于测试装置的装置可以包括具有多个探针的探针卡组件，每个探针具有用于接触要测试的装置的尖端，并且具有根据本发明的预选的一组或多个特征在探针卡组件安装在其中之后将探针卡组件对准的选择标准。在一些实施例中，所识别的一组一个或多个特征的身份可以被传送到探测器，以促进探针卡组件的全局对准，其最小化探针卡组件中的所有尖端的聚集失准

9. 发明授权

US5883788A Backing plate for LGA mounting of integrated circuits facilitates probing of the IC's pins 失效
标题翻译：用于LGA安装集成电路的背板有助于IC引脚的探测
公开(公告)号：US5883788A
公开(公告)日：1999-03-16
申请号：US741649
申请日：1996-10-31
申请人： Douglas S. Ondricek , Terrel L. Morris , Eric C. Peterson
发明人： Douglas S. Ondricek , Terrel L. Morris , Eric C. Peterson
IPC分类号： H05K1/14 , G01R1/04 , G01R1/073 , H01L23/32 , H05K7/12 , H01R9/09
CPC分类号： G01R1/07314 , G01R1/0483
摘要： A backing plate facilitates electrical probing of VLSI IC signals in an array of signal via pads on the back side of a printed circuit board and which correspond to an LGA of socket pads on the front side of the printed circuit board. The backing plate is constructed of electrically non conductive mechanically stiff material that already has drilled therein a hole for each signal via pad that might be probed. Polyamide is a suitable material for such a backing plate. Special symbols, legends and suitable grid identification axes can be silk screened onto the side of the backing plate that remains visible when installed. The drilled insulative backing plate can be equipped with captive threaded studs, if desired. Alternatively, it may simply have holes to receive fasteners, or have captive female threaded fasteners in lieu of holes.
摘要翻译：背板有助于在印刷电路板背面的信号通孔焊盘阵列中对VLSI IC信号进行电探测，并且其对应于印刷电路板正面上的插座焊盘的LGA。背板由非导电的机械刚性材料构成，其已经在其中钻有用于可能被探测的每个信号通孔垫的孔。聚酰胺是这种背板的合适材料。特殊符号，图例和合适的网格识别轴可以丝网印刷到背板上，安装时仍然可见。如果需要，钻孔的绝缘背板可以装有固定螺柱。或者，它可以简单地具有用于接收紧固件的孔，或者具有用于代替孔的固定内螺纹紧固件。

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