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1. 发明授权

US07222311B2 Method and apparatus for interconnect-driven optimization of integrated circuit design 有权
标题翻译：用于集成电路设计的互连驱动优化的方法和装置
公开(公告)号：US07222311B2
公开(公告)日：2007-05-22
申请号：US10387644
申请日：2003-03-12
申请人： Douglas Kaufman , Hazem Almusa , Vinay Srinivas , Donald V. Organ , Larry Ke , Wei Li , Japinder Singh , Robert Mathews
发明人： Douglas Kaufman , Hazem Almusa , Vinay Srinivas , Donald V. Organ , Larry Ke , Wei Li , Japinder Singh , Robert Mathews
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.
摘要翻译：提供了用于集成电路的布局后优化的方法和装置。在一种情况下，仅提供通过对放置和路由的增量更改实现的本地变换，以避免需要重新合成，重新放置和重新路由的昂贵的设计迭代循环。可以在多个优化阶段中提供优化，每个优化阶段都完成一组指定的转换。在每组局部变换结束时执行静态时序分析，以确定是否需要进一步的优化步骤。在一种情况下，首先对物理设计进行扫描，以了解驱动器和负载之间的不匹配。然后，在第二优化阶段，使用“双向组合式总负空闲”（BCTNS）算法来识别物理设计中的“热点”用于局部变换。在后续阶段，执行基于关键路径中的会议建立时间和保持时间的优化。

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