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1. 发明授权

US06512989B1 Generating and controlling analog and digital signals on a mixed signal test system 失效
标题翻译：在混合信号测试系统上生成和控制模拟和数字信号
公开(公告)号：US06512989B1
公开(公告)日：2003-01-28
申请号：US09276849
申请日：1999-03-26
申请人： Mark Deome , Donald V. Organ
发明人： Mark Deome , Donald V. Organ
IPC分类号： G06F1900
CPC分类号： G01R31/31917 , G01R31/3167
摘要： An automated test system that has analog and digital resources for testing mixed signal ICs. A control pattern is provided that is used by the automated test system to simultaneously control both the digital resources and the analog resources. The control pattern is comprised of a sequentially executed two-dimensional array with columns corresponding to analog and digital resources. The automated test system uses the control pattern to control both the analog and digital resources.
摘要翻译：具有用于测试混合信号IC的模拟和数字资源的自动化测试系统。提供了一种由自动测试系统用于同时控制数字资源和模拟资源的控制模式。控制模式由具有对应于模拟和数字资源的列的顺序执行的二维阵列组成。自动测试系统使用控制模式来控制模拟和数字资源。

2. 发明授权

US07222311B2 Method and apparatus for interconnect-driven optimization of integrated circuit design 有权
标题翻译：用于集成电路设计的互连驱动优化的方法和装置
公开(公告)号：US07222311B2
公开(公告)日：2007-05-22
申请号：US10387644
申请日：2003-03-12
申请人： Douglas Kaufman , Hazem Almusa , Vinay Srinivas , Donald V. Organ , Larry Ke , Wei Li , Japinder Singh , Robert Mathews
发明人： Douglas Kaufman , Hazem Almusa , Vinay Srinivas , Donald V. Organ , Larry Ke , Wei Li , Japinder Singh , Robert Mathews
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.
摘要翻译：提供了用于集成电路的布局后优化的方法和装置。在一种情况下，仅提供通过对放置和路由的增量更改实现的本地变换，以避免需要重新合成，重新放置和重新路由的昂贵的设计迭代循环。可以在多个优化阶段中提供优化，每个优化阶段都完成一组指定的转换。在每组局部变换结束时执行静态时序分析，以确定是否需要进一步的优化步骤。在一种情况下，首先对物理设计进行扫描，以了解驱动器和负载之间的不匹配。然后，在第二优化阶段，使用“双向组合式总负空闲”（BCTNS）算法来识别物理设计中的“热点”用于局部变换。在后续阶段，执行基于关键路径中的会议建立时间和保持时间的优化。

3. 发明授权

US06449741B1 Single platform electronic tester 有权
标题翻译：单平台电子测试仪
公开(公告)号：US06449741B1
公开(公告)日：2002-09-10
申请号：US09183038
申请日：1998-10-30
申请人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： H02H305
CPC分类号： G01R1/025 , G01R31/2834 , G01R31/319
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
摘要翻译：一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。测试头耦合到被测设备。被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。存储器测试电路将内存测试模式应用到与测试头耦合的待测器件，并响应于存储器测试模式接收来自被测器件的存储器输出。测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号，单独记忆测试信号，或混合数字，模拟和存储器测试信号。测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。

4. 发明授权

US06332212B1 Capturing and displaying computer program execution timing 失效
标题翻译：捕获和显示计算机程序执行时间
公开(公告)号：US06332212B1
公开(公告)日：2001-12-18
申请号：US08944935
申请日：1997-10-02
申请人： Donald V. Organ , Mark E. Deome , Rajaneekara Techasaratoole , Val N. Greene
发明人： Donald V. Organ , Mark E. Deome , Rajaneekara Techasaratoole , Val N. Greene
IPC分类号： G06F945
CPC分类号： G06F11/323 , G06F11/3419 , G06F2201/86
摘要： A software tool for analyzing the real-time performance characteristics of computer programs. A subprogram automatically records the execution time at a large number of pre-identified points in the code to be analyzed. This time information is captured in real-time and is minimally invasive. The display is subsequently displayed using a timing diagram display tool for a graphical user interface. The displayed timing diagrams provides a visual representation of the execution of the software in time, and provides a user to scale the time or show the profile in an alternate perspective. The present invention further provides a graphical representation of the hierarchical execution of subroutines and program modules within the software by displaying the nested execution of the software.
摘要翻译：一种用于分析计算机程序的实时性能特征的软件工具。子程序自动将执行时间记录在要分析的代码中的大量预先识别的点上。该时间信息被实时捕获并且是微创的。随后使用图形用户界面的时序图显示工具显示显示。显示的时序图提供了软件在时间上的可视化表示，并为用户提供了时间缩放或以备选视角显示配置文件。本发明还通过显示软件的嵌套执行来提供软件内的子程序和程序模块的分级执行的图示。

5. 发明授权

US06591407B1 Method and apparatus for interconnect-driven optimization of integrated circuit design 有权
公开(公告)号：US06591407B1
公开(公告)日：2003-07-08
申请号：US09516489
申请日：2000-03-01
申请人： Douglas Kaufman , Hazem Almusa , Vinay Srinivas , Donald V. Organ , Larry Ke , Wei Li , Japinder Singh , Robert Mathews
发明人： Douglas Kaufman , Hazem Almusa , Vinay Srinivas , Donald V. Organ , Larry Ke , Wei Li , Japinder Singh , Robert Mathews
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5068
摘要： A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

6. 发明授权

US07191368B1 Single platform electronic tester 失效
标题翻译：单平台电子测试仪
公开(公告)号：US07191368B1
公开(公告)日：2007-03-13
申请号：US09938157
申请日：2001-08-22
申请人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： G06F11/00
CPC分类号： G01R1/025 , G01R31/2834 , G01R31/319
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
摘要翻译：一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。测试头耦合到被测设备。被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。存储器测试电路将内存测试模式应用到与测试头耦合的待测器件，并响应于存储器测试模式接收来自被测器件的存储器输出。测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号，单独记忆测试信号，或混合数字，模拟和存储器测试信号。测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。

7. 发明授权

US07047463B1 Method and system for automatically determining a testing order when executing a test flow 有权
标题翻译：执行测试流程时自动确定测试顺序的方法和系统
公开(公告)号：US07047463B1
公开(公告)日：2006-05-16
申请号：US10642000
申请日：2003-08-15
申请人： Donald V. Organ , Richard C. Dokken
发明人： Donald V. Organ , Richard C. Dokken
IPC分类号： G01R31/28
CPC分类号： G01R31/2893 , G01R31/2834
摘要： A method and system for automated multisite testing. Specifically, in one embodiment, a method is disclosed for determining a testing order of plurality of testing operations of a test flow in a multisite testing environment. The method begins by automatically walking through the test flow by performing recursion on the plurality of testing operations. Next, the method automatically assigns a plurality of relative priorities to the plurality of testing operations. The plurality of relative priorities determine the testing order used when executing each of the plurality of testing operations in said test flow. Each of the plurality of testing operations is executed only once when testing a plurality of devices under test (DUTs) in the multisite testing environment.
摘要翻译：一种用于自动多站点测试的方法和系统。具体地，在一个实施例中，公开了一种用于确定多站点测试环境中的测试流的多个测试操作的测试顺序的方法。该方法通过在多个测试操作上执行递归来自动走过测试流程。接下来，该方法自动地将多个相对优先级分配给多个测试操作。多个相对优先级确定在执行所述测试流程中的多个测试操作中的每一个时使用的测试顺序。当在多站点测试环境中测试多个待测设备（DUT）时，多个测试操作中的每一个仅执行一次。

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