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1. 发明授权

US06332188B1 Digital signal processor with bit FIFO 有权
标题翻译：具有位FIFO的数字信号处理器
公开(公告)号：US06332188B1
公开(公告)日：2001-12-18
申请号：US09187479
申请日：1998-11-06
申请人： Douglas Garde , Alexei Zatsman , Aryeh Lezerovitz , Zvi Greenfield , David R. Levine , Jose Fridman
发明人： Douglas Garde , Alexei Zatsman , Aryeh Lezerovitz , Zvi Greenfield , David R. Levine , Jose Fridman
IPC分类号： G06F9315
CPC分类号： G06F9/30018 , G06F9/30 , G06F9/30032 , G06F9/30101
摘要： A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.
摘要翻译：数字信号处理器包括具有算术逻辑单元，乘法器，移位器和寄存器文件的计算块。计算块包括用于以位格式存储指令和操作数作为连续比特流的多个寄存器，并且利用比特传送机制在单个周期内传送多个寄存器之间的任意比特长度的比特字段和移位器多个寄存器可以是位于寄存器文件中的通用寄存器。寄存器文件还可以包括至少一个控制信息寄存器，用于存储比特传送机制使用的控制信息。

2. 发明授权

US07333530B1 Despread signal recovery in digital signal processors 有权
标题翻译：数字信号处理器中的扩展信号恢复
公开(公告)号：US07333530B1
公开(公告)日：2008-02-19
申请号：US09925889
申请日：2001-08-06
申请人： Rasekh Rifaat , Zvi Greenfield , Jose Fridman
发明人： Rasekh Rifaat , Zvi Greenfield , Jose Fridman
IPC分类号： H04B1/707
CPC分类号： H04B1/7093
摘要： A digital signal processor performs despread decoding in wireless telephone systems. Orthogonal codes are used to combine data signals into one overall coded signal which is transmitted. The orthogonal codes are used to retrieve individual data signals from the transmitted overall coded signal. Despread instructions are included in the digital signal processor functionality.
摘要翻译：数字信号处理器在无线电话系统中执行解扩解码。正交码用于将数据信号组合成一个发送的总编码信号。正交码用于从发送的总体编码信号中检索单个数据信号。解扩指令包括在数字信号处理器功能中。

3. 发明授权

US07069388B1 Cache memory data replacement strategy 有权
标题翻译：缓存内存数据替换策略
公开(公告)号：US07069388B1
公开(公告)日：2006-06-27
申请号：US10616549
申请日：2003-07-10
申请人： Zvi Greenfield , Dina Treves , Gil Zukerman
发明人： Zvi Greenfield , Dina Treves , Gil Zukerman
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/0804 , G06F12/0864
摘要： A method for caching specified data in an n-way set associative memory with a copy-back update policy consists of the following steps. First, a row of the associative memory, organized as a plurality of rows and having n ways per row, is selected according to the main memory address of the specified data. The main memory provides primary storage for the data being cached. If one of the ways of the selected row holds invalid data, the specified data is cached in the way holding the invalid data and the data caching process is discontinued. If all n ways of the selected row hold valid data, the following steps are performed. First, a replacement strategy is used to select a way from the selected row. If the way selected in accordance with the replacement strategy holds unmodified data, the specified data is cached in the way selected by the replacement strategy and the data caching process is discontinued. However, if the way selected by the replacement strategy holds modified data, the ways of the selected row are examined again to find a way that holds data from the currently open page of the main memory. If such at least one such way is found, the specified data is cached in one of the ways holding data from the open page, and the data caching process is discontinued. Finally, if none of the ways in the selected row meet the above criteria, the specified data is cached in the way previously selected by the replacement algorithm, and the method terminates.
摘要翻译：用于在具有复制更新策略的n路组合关联存储器中缓存指定数据的方法包括以下步骤。首先，根据指定数据的主存储器地址选择一行组织为多行并且每行具有n个方式的一行。主内存为正在缓存的数据提供主存储。如果所选行的一种方式存在无效数据，则以保持无效数据的方式缓存指定的数据，并停止数据缓存过程。如果所选行的所有n种方式都保存有效数据，则执行以下步骤。首先，使用替换策略来从所选行中选择一种方式。如果根据替换策略选择的方式保存未修改的数据，则以替换策略选择的方式缓存指定的数据，并停止数据缓存过程。然而，如果由替换策略选择的方式保存修改的数据，则再次检查所选行的方式以找到保存来自主存储器的当前打开页面的数据的方式。如果发现至少一种这样的方式，则以保持来自打开页面的数据的方式之一缓存指定的数据，并且停止数据高速缓存处理。最后，如果所选行中没有一个符合上述条件的方式，则以先前由替换算法选择的方式缓存指定的数据，并且该方法终止。

4. 发明授权

US06389497B1 DRAM refresh monitoring and cycle accurate distributed bus arbitration in a multi-processing environment 有权
标题翻译：在多处理环境中，DRAM刷新监视和循环精确的分布式总线仲裁
公开(公告)号：US06389497B1
公开(公告)日：2002-05-14
申请号：US09235780
申请日：1999-01-22
申请人： Robert Koslawsky , Zvi Greenfield , Alberto E. Sandbank
发明人： Robert Koslawsky , Zvi Greenfield , Alberto E. Sandbank
IPC分类号： G06F1314
CPC分类号： G11C11/406 , G06F13/368
摘要： A multiprocessor system includes a distributed bus arbitration system in which bus arbitration takes place simultaneously on each of the multiple processors connected to the bus. Each processor has a local arbitrator of common configuration with the other local arbitrators and a dedicated request line. Each local arbitrator is connected to each dedicated request line to monitor signals on lines indicative of requests for mastership of the bus by the processors. Since each local arbitrator is of common configuration with the other local arbitrators, is operating synchronously with the other arbitrators, and is provided with a similar set of inputs, each arbitrator will arrive at the same conclusion as to which processor is to become bus master. Accordingly, an external bus arbitrator is not required and acknowledge lines are not required to communicate signals indicative of the result of the bus arbitration to the processors. Additionally, the number of priority request lines can be dramatically reduced by requiring a requesting processor to de-assert a bus request upon detecting a priority request by another processor. The multi processor system also includes a distributed DRAM refresh system in which each processor has a local DRAM refresh controller of common configuration with the other DRAM refresh controllers. Signals on a refresh line are monitored by each of the local DRAM refresh controllers to enable synchronous updating of local DRAM refresh counters and resets of the local DRAM refresh counters. Thus, as mastership of the bus passes from one processor to the other, the new bus master's local DRAM refresh controller can continue the DRAM refresh process without requiring information to be transferred from the old bus master to the new bus master, and without duplicating DRAM refresh operations.
摘要翻译：多处理器系统包括分布式总线仲裁系统，其中总线仲裁同时发生在连接到总线的多个处理器中的每个处理器上。每个处理器具有与其他本地仲裁器和专用请求行的共同配置的本地仲裁器。每个本地仲裁器连接到每个专用请求线，以监视由处理器指示总线占用的请求的线路上的信号。由于每个本地仲裁员与其他本地仲裁员具有共同的配置，与其他仲裁员同步工作，并且提供了类似的一组输入，每个仲裁员将得到与哪个处理器将成为总线主机相同的结论。因此，不需要外部总线仲裁器，并且不需要确认线路来将指示总线仲裁结果的信号传送给处理器。此外，通过要求请求处理器在检测到另一个处理器的优先级请求时，去除总线请求，可以大大减少优先级请求线的数量。多处理器系统还包括分布式DRAM刷新系统，其中每个处理器具有与其它DRAM刷新控制器共同配置的本地DRAM刷新控制器。刷新线路上的信号由本地DRAM刷新控制器中的每一个进行监视，以实现本地DRAM刷新计数器的同步更新和本地DRAM刷新计数器的复位。因此，随着总线的主管从一个处理器传递到另一个处理器，新的总线主控器的本地DRAM刷新控制器可以继续DRAM刷新过程，而不需要将信息从旧总线主机传送到新的总线主机，而不需要复制DRAM 刷新操作。

5. 发明授权

US07661059B2 High performance turbo and Viterbi channel decoding in digital signal processors 有权
标题翻译：数字信号处理器中的高性能Turbo和Viterbi通道解码
公开(公告)号：US07661059B2
公开(公告)日：2010-02-09
申请号：US09923225
申请日：2001-08-06
申请人： Stephen J. Plante , Zvi Greenfield
发明人： Stephen J. Plante , Zvi Greenfield
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , G06F9/30003 , G06F9/3001 , G06F9/3895 , G06F17/10 , H03M13/3911 , H03M13/4107 , H03M13/6511 , H03M13/6569
摘要： A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.
摘要翻译：数字信号处理器在无线系统中执行turbo和Virterbi信道解码。数字信号处理器的计算块具有用于执行与网格计算相关联的指令的加速器。 ACS指令执行α和β度量的网格计算。可以响应于单个指令执行多个蝶式计算。 TMAX指令用于计算网格的对数似然比。

6. 发明授权

US06618777B1 Method and apparatus for communicating between multiple functional units in a computer environment 有权
公开(公告)号：US06618777B1
公开(公告)日：2003-09-09
申请号：US09235025
申请日：1999-01-21
申请人： Zvi Greenfield
发明人： Zvi Greenfield
IPC分类号： G06F1314
CPC分类号： G06F13/1684 , G06F13/1605
摘要： A CPU includes a number of functional units that cooperate together to execute instructions. On-chip memory is divided into several sections, each of which is connected to an associated internal bus. All of the functional units are connected to each of the internal busses so that each of the functional units can read from and write to all memory locations. To conduct a transaction with memory, a functional unit determines which memory location it requires, and then arbitrates for mastership of the bus associated with the section of memory containing that memory location. By providing two or more internal busses, two or more bus transactions can occur simultaneously. A virtual bus is provided to facilitate transactions between functional units. The virtual bus is a bus arbiter without an associated physical bus. To conduct a transaction with another functional unit, the functional unit arbitrates for mastership of the virtual bus, the virtual bus monitors the internal busses or communicates with the other bus arbiters to determine which of the internal busses is unoccupied and, upon receiving a request to access the virtual bus, assigns one of the internal busses to the requesting functional unit. Using a virtual bus is advantageous since requesting access to the virtual bus has the affect of arbitrating for each of the physical busses simultaneously. Thus, the amount of time spent arbitrating for access to the physical busses is minimized. Also, since the physical busses typically do not run at 100% capacity, allocating use of the physical busses to non-memory transactions maximizes use of the physical busses without significantly distracting from the ability of the functional units to access memory. Finally, using a virtual bus instead of an additional physical bus takes up much less space than would be required if a dedicated physical bus were provided for transactions between functional units.

7. 发明申请

US20070204107A1 Cache memory background preprocessing 审中-公开
标题翻译：高速缓存内存背景预处理
公开(公告)号：US20070204107A1
公开(公告)日：2007-08-30
申请号：US11637232
申请日：2006-12-11
申请人： Zvi Greenfield , Yariv Saliternik
发明人： Zvi Greenfield , Yariv Saliternik
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0864
摘要： A cache memory preprocessor prepares a cache memory for use by a processor. The processor accesses a main memory via a cache memory, which serves a data cache for the main memory. The cache memory preprocessor consists of a command inputter, which receives a multiple-way cache memory processing command from the processor, and a command implementer. The command implementer performs background processing upon multiple ways of the cache memory in order to implement the cache memory processing command received by the command inputter.
摘要翻译：高速缓存存储器预处理器准备高速缓存以供处理器使用。处理器通过高速缓存存储器来访问主存储器，缓存存储器为主存储器提供数据高速缓存。缓存存储器预处理器由从处理器接收多路高速缓冲存储器处理命令的命令输入器和命令实现器组成。命令实现者通过高速缓冲存储器的多种方式执行后台处理，以实现由命令输入器接收的缓存存储器处理命令。

8. 发明申请

US20050198439A1 Cache memory prefetcher 审中-公开
标题翻译：缓存内存预取器
公开(公告)号：US20050198439A1
公开(公告)日：2005-09-08
申请号：US10793561
申请日：2004-03-04
申请人： Fredy Lange , Zvi Greenfield , Alberto Mandler , Avi Plotnik
发明人： Fredy Lange , Zvi Greenfield , Alberto Mandler , Avi Plotnik
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A prefetcher performs advance retrieval of data from a main memory, and places the retrieved data in an intermediate memory. The main memory is accessed by vector addressing, in which the vector access instruction includes a main memory address and a direction indicator. Main memory data is cached in an associated cache memory. The prefetcher contains a direction selector and a controller. The direction selector selects a direction of data access according to the direction indicator of a single data access transaction. The direction indicator is supplied by the processor accessing the main memory, and incorporates the processor's internal knowledge of the expected direction of future data accesses. The controller retrieves data items from the main memory, in the direction of access selected by the direction selector, and places the retrieved data items in the intermediate memory.
摘要翻译：预取器执行从主存储器的数据的提前检索，并将检索的数据放置在中间存储器中。主存储器由向量寻址访问，其中向量访问指令包括主存储器地址和方向指示符。主存储器数据被缓存在相关联的高速缓冲存储器中。预取器包含方向选择器和控制器。方向选择器根据单个数据访问事务的方向指示器来选择数据访问的方向。方向指示器由访问主存储器的处理器提供，并且包含处理器对未来数据访问的预期方向的内部知识。控制器从方向选择器选择的访问方向从主存储器检索数据项，并将检索到的数据项放置在中间存储器中。

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